Scan driving circuit and display device including the same

ABSTRACT

A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal ST p+1  of a p+1&#39;th shift register is situated between the start and end of a start pulse of the output signal ST p  of a p&#39;th shift register, and one each of a first enable signal through a Q&#39;th enable signal exist in sequence between the start of the start pulse of the output signal ST p  and the start of the start pulse of the output signal ST p+1 . The operations of a (p′, q)&#39;th NAND circuit are restricted based on period identifying signals, such that the NAND circuit generates scanning signals based only on a portion of the output signal STP corresponding to the first start pulse, the signal obtained by inverting the output signal ST p+1 , and the q&#39;th enable signal EN q .

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a scan driving circuit and to a displaydevice including the scan driving circuit. More particularly, thepresent invention relates to a scan driving circuit and to a displaydevice including the scan driving circuit, in which signals can besupplied to scanning lines, initialization control lines, and displaycontrol lines, and a lit/unlit state of display elements can be switchedmultiple times during one field period by supplying multiple pulsesignals to the display control lines during the field period, withoutaffecting the signals being supplied to the scanning lines andinitialization control lines.

2. Description of the Related Art

Examples of widely used display devices having display elements arrangedin the form of a two-dimensional matrix include liquid crystal displaydevices made up of liquid crystal cells driven by voltage, and alsodisplay devices including light emitting units which emit light underapplication of electric current (e.g., organic electroluminescence lightemitting units) and driving circuits for driving the light emittingunits.

The luminance of display elements including light emitting units whichemit light under application of electric current is controlled by thevalue of the current flowing through the light emitting units. In thesame way as with liquid crystal display devices, such display deviceshaving these display elements (e.g., organic electroluminescence displaydevices) can be driven by the simple matrix method and the active matrixmethod. While the active matrix method has shortcomings such as greatercomplexity in structure as compared with the simple matrix method, thereare also various advantages, such as being capable of higher luminance.

Various types of driving circuits configured from transistors andcapacitance units are in widespread use as circuits for driving a lightemitting unit by the active matrix method. For example, JapaneseUnexamined Patent Application Publication No. 2005-31630 discloses adisplay element configured of an organic electroluminescence lightemitting unit and a driving circuit, and a driving method thereof. Thisdriving circuit is a driving circuit configured of six transistors andone capacitance unit (hereinafter referred to as “6Tr/1C drivingcircuit”). FIG. 26 illustrates an equivalent circuit to a drivingcircuit (6Tr/1C driving circuit) of a display element of the m'th rowand n'th column in a display device configured of display elementsarrayed in the form of a two-dimensional matrix. Note that in thedescription, the display elements are assumed to be scanned in linesequence.

The 6Tr/1C driving circuit has a write transistor TR_(W), a drivingtransistor TR_(D), a capacitance unit C₁, and also a first transistorTR₁, a second transistor TR₂, a third transistor TR₃, and a fourthtransistor TR₄.

At the write transistor TR_(W), one source/drain region is connected toa data line DTL_(n), and the gate electrode is connected to a scanningline SCL_(m). At the driving transistor TR_(D), one source/drain regionis connected to the other source/drain region of the write transistorTR_(W), thereby configuring a first node ND₁. One end of the capacitanceunit C₁ is connected to a power supply line PS₁. At the capacitance unitC₁, a predetermined reference voltage (later-described voltage V_(CC) inthe example shown in FIG. 26) is applied to one end, and the other endis connected to the gate electrode of the driving transistor TR_(D),thereby configuring a second node ND₂. The scanning line SCL_(m) isconnected to an unshown scanning circuit, and the data line DTL_(n) isconnected to a signal output circuit 100.

At the first transistor TR₁, one source/drain region is connected to thesecond node ND₂, and the other source/drain region is connected to theother source/drain region of the driving transistor TR_(D). The firsttransistor TR₁ makes up a switch circuit portion connected between thesecond node ND₂ and the other source/drain region of the drivingtransistor TR_(D).

At the second transistor TR₂, one source/drain region is connected to apower supply line PS₃ to which is applied a predetermined initializingvoltage V_(Ini) (e.g., −4 volts) for initialization of the potential ofthe second node ND₂, and the other source/drain region is connected tothe second node ND₂. The second transistor TR₂ makes TR₁ makes up aswitch circuit portion connected between the second node ND₂ and thepower supply line PS₃ to which is applied the predetermined initializingvoltage V_(Ini).

At the third transistor TR₃, one source/drain region is connected to apower supply line PS₁ to which is applied a predetermined drivingvoltage V_(CC) (e.g., 10 volts), and the other source/drain region isconnected to the first node ND₁. The third transistor TR₃ makes up aswitch circuit portion connected between the first node ND₁ and thepower supply line PS₁ to which is applied the predetermined drivingvoltage V_(CC).

At the fourth transistor TR₄, one source/drain region is connected tothe other source/drain region of the driving transistor TR_(D), and theother source/drain region is connected to one end of a light emittingunit ELP (more specifically, the anode electrode of the light emittingunit ELP). The fourth transistor TR₄ makes up a switch circuit portionconnected between the other source/drain region of the drivingtransistor TR_(D) and one end of the light emitting unit ELP.

The gate electrode of the write transistor TR_(W) and the gate electrodeof the first transistor TR₁ are connected to the scanning line SCL_(m).The gate electrode of the second transistor TR₂ is connected to aninitialization control line AZ_(m). Scanning signal supplied to anunshown scanning line SCL_(m−1) scanned immediately prior to thescanning line SCL_(m) is also supplied to the initialization controlline AZ_(m). The gate electrodes of the third transistor TR₃ and thefourth transistor TR₄ are connected to a display control line CL_(m) forcontrolling the lit/unlit state of the display element.

For example, each transistor is formed as a p-channel thin-filmtransistor (TFT), with the light emitting unit ELP provided on aninterlayer-insulating later or the like, formed so as to cover thedriving circuit. At the light emitting unit ELP, the anode electrode isconnected to the other source/drain region of the fourth transistor TR₄,and the cathode electrode is connected to a power supply line PS₂.Voltage V_(Cat) (e.g., −10 volts) is applied to the cathode electrode ofthe light emitting unit ELP. Symbol C_(EL) represents the capacitance ofthe light emitting unit ELP.

Now, when configuring transistors of TFTs, irregularity in thresholdvoltage is unavoidable to a certain extent. In the event that there isirregularity in the amount of current flowing through the light emittingunit ELP due to irregularity in the threshold value of the drivingtransistor TR_(D), the uniformity of luminance of the display devicesuffers. Accordingly, an arrangement has to be made where the amount ofcurrent flowing through the light emitting unit ELP is not affected byirregularity in the threshold value of the driving transistor TR_(D). Asdescribed later, the light emitting unit ELP is driven so as to beunaffected by irregularity in the threshold value of the drivingtransistor TR_(D).

A driving method of a display element at the m'th row and n'th column ofa display device configured as a two-dimensional array of N×M displayelements will be described with reference to FIGS. 27A and 27B. FIG. 27Aillustrates a schematic timing chart of signals on the initializationcontrol line AZ_(m), scanning line SCL_(m), and display control lineCL_(m). FIGS. 27B through 28B schematically illustrate the on/off statesand the likes of the transistors of a 6Tr/1C driving circuit. Tofacilitate description, we will refer the period during which theinitialization control line AZ_(m) is scanned as the “m−1'th horizontalscan period”, and the period during which the scanning line SCL_(m) isscanned as the “m'th horizontal scan period”.

As shown in FIG. 27A, in the m−1'th horizontal scan period, aninitialization process is carried out, which will be described in detailwith reference to FIG. 27B. In the m−1'th horizontal scan period, theinitialization control line AZ_(m) goes from a high level to a lowlevel, and the display control line CL_(m) goes from a low level to ahigh level. Note that the scanning line SCL_(m) remains at the highlevel. Accordingly, during the m−1'th horizontal scan period, the writetransistor TR_(W), first transistor TR₁, third transistor TR₃, andfourth transistor TR₄ are in an off state, while the second transistorTR₂ is in an on state.

A predetermined initialization voltage V_(Ini) for initializing thepotential of the second node ND₂ is applied to the second node ND₂ viathe second transistor TR₂ which is in the on state. Accordingly, thepotential of the second node ND₂ is initialized.

Next, as shown in FIG. 27A, a video signal V_(Sig) is written in them'th horizontal scanning period. At this time, threshold voltagecanceling processing of the driving transistor TR_(D) is performed inconjunction. Specifically, the second node ND₂ and the othersource/drain region of the driving transistor TR_(D) are electricallyconnected, the video signal V_(Sig) is applied from the data lineDTL_(n) to the first node ND₁ via the write transistor TR_(W) which hasbeen placed in an on state due to the signal from the scanning lineSCL_(m), thereby changing the potential of the second node ND₂ toward apotential which can be calculated by subtracting the threshold voltageV_(th) of the driving transistor TR_(D) from the video signal V_(Sig).

More detailed description will be made with reference to FIGS. 27A and28A. In the m'th horizontal scanning period, the initialization controlline AZ_(m) goes from a low level to a high level, and the scanning lineSCL_(m) goes from a high level to a low level. Note that the displaycontrol line CL_(m) remains at the high level. Accordingly, at the m'thhorizontal scanning period, the write transistor TR_(W) and firsttransistor TR₁ are in an on state, while the second transistor TR₂,third transistor TR₃, and fourth transistor TR₄ are in an off state.

The second node ND₂ and the other source/drain region of the drivingtransistor TR_(D) are electrically connected via the first transistorTR₁ which is in an on state, and the video signal V_(Sig) from the dataline DT_(n) is applied to the first node ND₁ via the write transistorTR_(W) which is in an on state due to the signal from the scanning lineSCL_(m). Accordingly, the potential of the second node ND₂ changestoward a voltage which can be calculated by subtracting the thresholdvoltage V_(th) of the driving transistor TR_(D) from the video signalV_(Sig).

According to the above-described initialization process, if thepotential of the second node ND₂ has been initialized such that thedriving transistor TR_(D) is in an on state at the start of the m'thhorizontal scanning period, the potential of the second node ND₂ changestoward the potential of the video signal V_(Sig) which is applied to thefirst node ND₁. However, once the potential difference between the gateelectrode of the driving transistor TR_(D) and one source/drain regionthereof reaches V_(th), the driving transistor TR_(D) goes to an offstate. In this state, the potential of the second node ND₂ isapproximately (V_(Sig)−V_(th)).

Next, the light emitting unit ELP is driven by applying current to thelight emitting unit ELP via the driving transistor TR_(D).

More detailed description will be made with reference to FIGS. 27A and28B. At the end of the m'th horizontal scanning period, the scanningline SCL_(m) goes from a low level to a high level. Also, the displaycontrol line CL_(m) goes from a high level to a low level. Note that theinitialization control line AZ_(m) remains at the high level. The thirdtransistor TR₃ and fourth transistor TR₄ are in an on state, while thewrite transistor TR_(W), first transistor TR₁, and second transistor TR₂are in an off state.

Driving voltage V_(CC) is applied to one source/drain region of thedriving transistor TR_(D) via the third transistor TR₃ which is in an onstate. Also, the other source/drain region of the driving transistorTR_(D) and one end of the light emitting unit ELP are connected via thefourth transistor TR₄ which is in an on state.

The current flowing through the light emitting unit ELP is a draincurrent I_(ds) which flows from the source region of the drivingtransistor TR_(D) to the drain region thereof, so this can be expressedwith the following expression (A) assuming that the driving transistorTR_(D) operates ideally at the saturation region. As shown in FIG. 28B,the drain current I_(ds) is applied to the light emitting unit ELP, andthe light emitting unit ELP emits light at a luminance corresponding tothe value of the drain current I_(ds).I _(ds) =k·μ·(V _(gs) −V _(th))²  (A)where μ represents effective mobility, L represents channel length, Wrepresents channel width, V_(gs) represents voltage between the sourceregion and gate region of the driving transistor TR_(D), and C_(OX)represents(relative permittivity of gate insulation layer)×(permittivity ofvacuum)/(thickness of gate insulation layer)ink≡(½)·(W/L)·C _(OX).

Further, sinceV _(gs) ≈V _(CC)−(V _(Sig) −V _(th))   (B)holds, the above Expression (A) can be rewritten as follows.

$\begin{matrix}\begin{matrix}{I_{ds} = {k \cdot \mu \cdot \left( {V_{CC} - \left( {V_{Sig} - V_{th}} \right) - V_{th}} \right)^{2}}} \\{= {k \cdot \mu \cdot \left( {V_{CC} - V_{Sig}} \right)^{2}}}\end{matrix} & (C)\end{matrix}$

As can be clearly understood from the above Expression (C), thethreshold voltage V_(th) of the driving transistor TR_(D) has no bearingon the value of the drain current I_(ds). In other words, a draincurrent I_(ds) corresponding to the video signal V_(Sig) can be appliedto the light emitting unit ELP unaffected by the value of the thresholdvoltage V_(th) of the driving transistor TR_(D). With theabove-described driving method, irregularities in the threshold voltageV_(th) of the driving transistor TR_(D) do not affect the luminance ofthe display element.

SUMMARY OF THE INVENTION

For a display device having the above-described display elements tooperate, circuits have to be provided which supply signals to thescanning lines, initialization control lines, and display control lines.The circuits for supplying these signals are preferably circuits of anintegrated structure, from the perspective of reduction in layout areaof the circuits, and reduction of circuit costs. Also, enabling multiplepulse signals to be supplied to the display control lines within onefield circuit without affecting the signals supplied to the scanninglines and initialization control lines is preferable from theperspective of reducing flickering of the image displayed on the displaydevice.

It has been found desirable to provide a scan driving circuit capable ofsupplying signals to the scanning lines, initialization control lines,and display control lines, and capable of supplying multiple pulsesignals to the display control lines within one field circuit withoutaffecting the signals supplied to the scanning lines and initializationcontrol lines.

A display device according to an embodiment of the present inventionincludes:

(1) display elements arrayed in the form of a two-dimensional matrix;

(2) scanning lines, initialization control lines configured toinitialize the display elements, and display control lines configured tocontrol lit/unlit states of the display elements, the scanning lines,initialization control lines, and display control lines extending in afirst direction;

(3) data lines extending in a second direction different from the firstdirection; and

(4) a scan driving circuit.

A scan driving circuit according to the present invention, and alsoconfiguring the display device according to the present invention,includes:

(A) a shift register unit configured of P (wherein P is a natural numberof 3 or greater) stages of shift registers, to sequentially shift inputstart pulses and output output signals from each stage, and

(B) a logic circuit unit configured to operate based on output signalsfrom the shift register unit, and enable signals,

(C) where, with the output signals of a p'th (where p=1, 2, . . . P−1)stage shift register represented as ST_(p), the start of a start pulseof an output signal ST_(p+1) of a p+1'th shift register is situatedbetween the start and end of a start pulse of the output signal ST_(p),

(D) and where one each of a first enable signal through a Q'th enablesignal (where Q is a natural number of 2 or greater) exist in sequencebetween the start of the start pulse of the output signal ST_(p) and thestart of the start pulse of the output signal ST_(p+1),

(E) and wherein the logic circuit unit includes (P−2)×Q NAND circuits;

wherein a first start pulse through a U'th (where U is a natural numberof 2 or greater) start pulse are input to a first stage shift registerduring a period equivalent to one field period;

and wherein period identifying signals are input to the logic circuitunit to identify each period from a u'th (where u=1, 2, . . . U−1) startpulse in an output signal ST₁ to a u+1'th start pulse, and a period fromthe start of the U'th start pulse to the start of the first start pulsein the next frame;

and wherein, with a q'th enable signal (where q=1, 2, . . . Q−1)represented as EN_(q), a signal based on a period identifying signal,the output signal ST_(p), a signal obtained by inverting the outputsignal ST_(p+1), and the q'th enable signal EN_(q), are input to a (p′,q)'th NAND circuit;

and wherein the operations of the NAND circuit are restricted based onperiod identifying signals, such that the NAND circuit generatesscanning signals based only on a portion of the output signal ST_(p)corresponding to the first start pulse, the signal obtained by invertingthe output signal ST_(p+1), and the q'th enable signal EN_(q).

With the display device according to an embodiment of the presentinvention, with regard to a display element receiving supply of signalsbased on scanning signals from the (p′, q)'th NAND circuit (except for acase wherein (p′=1, q=1) via a scanning line,

a signal based on a scanning signal from a (p′−1, q′)'th NAND circuit inthe event that q=1 holds, and a signal based on a scanning signal from a(p′, q″)'th (wherein q″ is a natural number from 1 through (q−1)) NANDcircuit in the event that q>1 holds, are supplied from an initializationcontrol line connected to the display element, and

a signal based on the output signal ST_(p+1) from a p′+1'th shiftregister in the event that q=1 holds, and a signal based on an outputsignal ST_(p+2) from a p′+2'th shift register in the event that q>1holds, are supplied from a display control line connected to the displayelement.

Now, from the perspective of shortening the length of wiring from theinitialization control line to a predetermined NAND circuit, with adisplay element where signals based on scanning signals from the (p′,q)'th NAND circuit are supplied via a scanning line, a configuration ispreferable wherein a signal based on a scanning signal from a (p′−1,q′)'th NAND circuit in the event that q=1 holds, and signals based onscanning signals from a (p′, q−1)'th NAND circuit in the event that q>1holds, are supplied from an initialization control line connected to thedisplay element.

With a configuration wherein a first start pulse and a second startpulse are input to a first stage shift register within a periodequivalent to one field period, an arrangement may be made wherein aperiod identifying signals is a signal which is at a low level or a highlevel in a period from the start of the first start pulse to the startof the second start pulse, and is at a high level or a low level in aperiod from the start of the second start pulse to the start of thefirst start pulse in the next frame. Thus, two periods can be identifiedusing a single period identifying signal. Also, with a configurationwherein a first start pulse through a fourth start pulse are input to afirst stage shift register within a period equivalent to one fieldperiod, an arrangement may be made wherein the period identifying signalis configured of a first period identifying signal and a second periodidentifying signal, thereby enabling identifying of four periods withthe combination of high/low level of the first period identifying signaland second period identifying signal.

An arrangement may be made wherein, in a period including a period wherethe portion of the output signal ST_(p′) corresponding to the firststart pulse is applied, a signal based on the period identifying signalis applied to the input side of the (p′, q)'th NAND circuit, such that asignal based on the period identifying signal goes to a high level, butotherwise is at a low level. Note that in the event that the periodidentifying signal is configured of a first period identifying signaland a second period identifying signal, a signal based on the periodidentifying signal may be applied to the input side of the (p′, q)'thNAND circuit such that a signal based on the first period identifyingsignal and a signal based on the second period identifying signal bothgo to a high level only in the period including a period where theportion of the output signal ST_(p), corresponding to the first startpulse is applied. More specifically, it is sufficient for the periodidentifying signal to be input to the input side of the NAND circuit,either directly or via a NOR circuit, such that the above-describedconditions are satisfied. Accordingly, the operations of the (p′, q)'thNAND circuit are restricted, and the NAND circuit only generatesscanning signals based on the portion of the output signal ST_(p)corresponding to the first start pulse, the signal obtained by invertingthe output signal ST_(p+1), and the q'th enable signal EN_(q).

With the display device according to an embodiment of the presentinvention having the scan driving circuit according to an embodiment ofthe present invention, signals for the scanning lines, initializationcontrol lines, and display control lines, are supplied based on signalsfrom the scan driving circuit. Accordingly, reduction in layout area ofthe circuits and reduction of circuit costs can be realized. Values of Pand Q, and/or the value of U, should be set as appropriate for thespecifications and so forth of the scan driving circuit and displaydevice.

Also, with the display device according to an embodiment of the presentinvention, the display control lines are supplied with signals based onoutput signals from shift registers making up the scan driving circuit.With the scan driving circuit according to an embodiment of the presentinvention, a first start pulse through a U'th start pulse are input tothe first stage shift register in a period equivalent to one fieldperiod. However, scanning signals output from the NAND circuit are notaffected by the number of start pulses input to the first stage shiftregister. Accordingly, multiple pulse signals can be supplied to adisplay control line within one field period without affecting signalssupplied to scanning lines and initialization control lines, by a simplearrangement of changing the number of start pulses input to the firststage shift register.

Note that the scanning signals from the NAND circuit and the outputsignals from the shift register should be inverted as appropriate andthen supplied, depending on the polarity and the like of the transistorsmaking up the display element. The term “a signal based on a scanningsignal” may refer to the scanning signal itself, or may refer to asignal where the polarity of the scanning signal has been inverted. Inthe same way, the term “a signal based on an output signal from theshift register” may refer to the output signal from the shift registeritself, or may refer to a signal where the polarity of the output signalfrom the shift register has been inverted.

The scan driving circuit according to an embodiment of the presentinvention can be manufactured by widely-employed semiconductormanufacturing techniques. The shift registers making up the shiftregister unit, the NAND circuits and NOR circuits configuring the logiccircuit unit may be configurations and structures which are widelyemployed. The scan driving circuit may be configured as an independentcircuit, or may be configured integrally with the display device. Forexample, in the event that the display elements configuring the displaydevice have transistors, the scan driving circuit can be manufactured atthe same time with the process for manufacturing the display elements.

With the display device according to an embodiment including variouspreferred configurations, display elements of a configuration so as tobe scanned by signals from scanning lines and subjected to aninitialization process based on signals from initialization controllines, and further display elements of a configuration wherein displayperiods and non-display periods are switched by signals from displaycontrol lines, can be widely used.

The display elements configuring the display device according to anembodiment of the present invention may include:

(1-1) a driving circuit including a write transistor, a drivingtransistor, and a capacitance unit; and

(1-2) a light emitting unit to which current is applied via the drivingtransistor. The light-emitting unit may be configured of a lightemitting unit which emits light under application of electric current,examples of which include an organic electroluminescence unit, aninorganic electroluminescence unit, an LED light emitting unit, asemiconductor laser light emitting unit, and so forth. Of these, aconfiguration of light emitting units which are organicelectroluminescence units is preferable from the perspective ofconfiguring a flat display device for color display.

With the driving circuit configuring the display element as describedabove (hereinafter, may be referred to as “driving circuit configuringthe display element according to an embodiment of the presentinvention”), an arrangement may be made wherein,

with regard to the write transistor,

-   -   (a-1) one source/drain region is connected to the data line, and    -   (a-2) the gate electrode is connected to the scanning line;

and wherein, with regard to the driving transistor,

-   -   (b-1) one source/drain region is connected to the other        source/drain region of the write transistor, thereby configuring        a first node;

and wherein, with regard to the capacitance unit,

-   -   (c-1) a predetermined reference voltage is applied to one end        thereof, and    -   (c-2) the other end is connected with the gate electrode of the        driving transistor, thereby configuring a second node;

and wherein the write transistor is controlled by signals from thescanning line.

The driving circuit configuring the display element according to anembodiment of the present invention may further include

(d) a first switch circuit unit connected between the second node andthe other source/drain region of the driving transistor;

wherein the first switch circuit unit is controlled by signals from thescanning line.

The driving circuit configuring the display element including theabove-described preferred configuration of an embodiment of the presentinvention may further include

(e) a second switch circuit unit connected between the second node and apower supply line to which a predetermined initialization voltage isapplied;

wherein the second switch circuit unit is controlled by signals from theinitialization control line.

The driving circuit configuring the display element including theabove-described preferred configuration of an embodiment of the presentinvention may further include

(f) a third switch circuit unit connected between the first node and apower supply line to which a driving voltage is applied;

wherein the third switch circuit unit is controlled by signals from thedisplay control line.

The driving circuit configuring the display element including theabove-described preferred configuration of an embodiment of the presentinvention may further include

(g) a fourth switch circuit unit connected between the othersource/drain region of the driving transistor and one end of the lightemitting unit;

wherein the fourth switch circuit unit is controlled by signals from thedisplay control line.

With a display device having a driving circuit including theabove-described first switch circuit unit through fourth switch circuitunit, the light emitting unit may be driven by

(a) performing an initialization process of applying a predeterminedinitial voltage from a power supply line to a second node via the secondswitch circuit unit in an on state, following which the second switchcircuit unit is placed in an off state, thereby setting the potential ofthe second node to a predetermined reference potential;

(b) performing a writing process of maintaining the off state of thesecond switch circuit unit, third switch circuit unit, and fourth switchcircuit unit, while placing the first switch circuit unit in an onstate, and in a state where the second node and the other source/drainregion of the driving transistor are electrically connected by the firstswitch circuit unit in the on state, a video signal is applied to thefirst node form the data line via the write transistor placed in an onstate by a signal from the scanning line, thereby changing the potentialof the second node toward a potential which can be calculated bysubtracting the threshold voltage of the driving transistor from thevideo signal;

(c) subsequently placing the write transistor in an off state by asignal from the scanning line; and

(d) and subsequently maintaining the off state of the first switchcircuit unit and second switch circuit unit while electricallyconnecting the other source/drain region of the driving transistor toone end of the light emitting unit via the fourth switch circuit unit inthe on state, and applying a predetermined driving voltage to the firstnode from the power supply line via the third switch circuit unit in theon state, thereby applying current to the light emitting unit via thedriving transistor, and thus driving the light emitting unit.

With the driving circuit configuring the display device according to anembodiment of the present invention, a predetermined reference voltageis applied to one end of the capacitance unit, whereby the potential atthe one end of the capacitance unit is maintained when the displaydevice is operating. The value of the predetermined reference voltage isnot restricted in particular. For example, a configuration may be madewherein one end of the capacitance unit is connected to a power supplyline for applying predetermined voltage to the other end of the lightemitting unit, so that the predetermined voltage is applied as thereference voltage.

With the display device according to an embodiment of the presentinvention including the above-described various preferredconfigurations, the configurations and structures of various wiring suchas the scanning lines, initialization control lines, display controllines data lines, power supply lines, and so forth, may be ofconfigurations and structures widely in use. Also, the configuration andstructure of the light emitting unit may be of configurations andstructures widely in use. Specifically, in the case of forming the lightemitting unit as an organic electroluminescence light emitting unit, thelight emitting unit may be configured of an anode electrode, holetransporting layer, emissive layer, electron transporting layer, cathodeelectrode, and so forth. Also, the configuration and structure of thesignal output circuit connected to the data line, and so forth, may beof configurations and structures widely in use.

The display device according to an embodiment of the present inventionmay be of a so-called black-and-white display configuration, or may beof a configuration wherein each pixel is configured of multiplesub-pixels, specifically, a configuration wherein a pixel is confirmedof the three sub pixels of a red light emitting sub-pixel, a green lightemitting sub-pixel, and a blue light emitting sub-pixel. Further, apixel may be configured of a set where one type of multiple types ofsub-pixels are added to the above three types of sub pixels (e.g., a setwherein a sub-pixel emitting white light is added for improvingluminance, set wherein a sub-pixel emitting a complementary color isadded for expanding the range of color reproduction, a set wherein asub-pixel emitting yellow light is added for expanding the range ofcolor reproduction, a set wherein sub-pixels emitting yellow and cyanlight are added for expanding the range of color reproduction).

Examples of image display resolution regarding the number of pixels ofthe display device include, but are not restricted to, VGA (640, 480),S-VGA (800, 600), XGA (1024, 768), APRC (1152, 900), S-XGA (1280, 1024),U-XGA (1600, 1200), HD-TV (1920, 1080), Q-XGA (2048, 1536) and so forth,and also (1920, 1035), (720, 480), (1280, 960) and so forth. In the caseof a black-and-white display device, basically, display elements of thesame number as the number of pixels are formed in matrix fashion. In thecase of a color display device, basically, display elements threefoldthe number of pixels are formed in matrix fashion. The display elementsmay be formed in a striped array, or in a delta array, and should bearrayed as appropriate in accordance with the design of the displaydevice.

With the driving circuit making up the display element according to anembodiment of the present invention, the write transistor and drivingtransistor may be configured of p-channel type thin-film transistors(TFT), for example. Note that the write transistor may be an n-channeltype instead. The first switch circuit unit, second switch circuit unit,third switch circuit unit, and fourth switch circuit unit may beconfigured of widely-used switching devices such as TFTs, and may bep-channel type TFTs or n-channel type TFTs, for example.

With the driving circuit making up the display element according to anembodiment of the present invention, the capacitance unit making up thedriving circuit may be configured of one electrode, another electrode,and a dielectric layer (insulating layer) between these electrodes. Thetransistors and capacitance unit making up the driving circuit may beformed within a certain plane, and formed on a supporting body, forexample. In the event that the light emitting unit is to be an organicelectroluminescence light emitting unit, the light emitting unit may beformed above the transistors and capacitance unit making up the drivingcircuit. Also, the other source/drain region of the driving transistormay be connected to one end of the light emitting unit (anode electrodeprovided to the light emitting unit, etc.) via another transistor, forexample. Also note that a configuration may be employed whereintransistors are formed on a semiconductor substrate.

Note that in the Present Specification, the term “one source/drainregion” may be used regarding the one of the two source/drain regionswhich a transistor has, which is connected to the power source side.Also, the term that a transistor is in an “on state” means that achannel is formed between the source/drain regions, regardless ofwhether or not current is flowing from one source/drain region to theother source/drain region. Conversely, the term that a transistor is inan “off state” means that no channel is formed between the source/drainregions. The expression that a source/drain region of a certaintransistor is connected to a source/drain region of another transistormeans that the source/drain region of the certain transistor and thesource/drain region of the other transistor occupy the same region.Further, the source/drain regions are not restricted to being configuredof impurity-doped polysilicon, amorphous silicon, and the like, and mayalso be configured of layered strictures thereof, or layers of organicmaterial (electroconductive polymers). Moreover, in the timing chartsused for description in the Present Specification, it should be notedthat the length of the horizontal axis representing periods (length oftime) is a schematic representation, not necessarily indicating theratio of duration of the time periods.

With the display device according to an embodiment of the presentinvention having the scan driving circuit according to an embodiment ofthe present invention, signals for the scanning lines, initializationcontrol lines, and display control lines, are supplied based on signalsfrom the scan driving circuit. Accordingly, reduction in layout area ofthe circuits and reduction of circuit costs can be realized.

With the scan driving circuit according to an embodiment of the presentinvention, multiple pulse signals can be supplied to a display controlline within one field period without affecting signals supplied toscanning lines and initialization control lines, by a simple arrangementof changing the number of start pulses input to the first stage shiftregister. Also, with the display device according to an embodiment ofthe present invention, flickering of the image displayed on the displaydevice can be reduced by a simple arrangement of changing the number ofstart pulses input to the first stage shift register configuring thescan driving circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a scan driving circuit according to afirst embodiment;

FIG. 2 is a conceptual diagram of a display device according to thefirst embodiment, including the scan driving circuit shown in FIG. 1;

FIG. 3 is a schematic timing chart of a shift register unit making upthe scan driving circuit shown in FIG. 1;

FIG. 4 is a schematic timing chart of an upstream stage of a logiccircuit unit making up the scan driving circuit shown in FIG. 1;

FIG. 5 is a schematic timing chart of a downstream stage of a logiccircuit unit making up the scan driving circuit shown in FIG. 1;

FIG. 6 is an equivalent circuit diagram of a driving circuit making up adisplay element at the m'th row and n'th column of the display deviceshown in FIG. 2;

FIG. 7 is a partial cross-sectional diagram of a portion of a displayelement making up the display device shown in FIG. 2;

FIG. 8 is a schematic driving timing chart of a display element at them'th row and n'th column;

FIGS. 9A and 9B are diagrams schematically illustrating the on/offstates of the transistors in the driving circuit making up the displayelement at the m'th row and n'th column;

FIGS. 10A and 10B are diagrams continuing from FIGS. 9A and 9B,schematically illustrating the on/off states of the transistors in thedriving circuit making up the display element at the m'th row and n'thcolumn;

FIGS. 11A and 11B are diagrams continuing from FIGS. 10A and 10B,schematically illustrating the on/off states of the transistors in thedriving circuit making up the display element at the m'th row and n'thcolumn;

FIGS. 12A and 12B are diagrams continuing from FIGS. 11A and 11B,schematically illustrating the on/off states of the transistors in thedriving circuit making up the display element at the m'th row and n'thcolumn;

FIG. 13 is a circuit diagram of a scan driving circuit according to acomparative example;

FIG. 14 is a timing chart of the scan driving circuit shown in FIG. 13regarding the leading edges of start pulses between the start and end ofa period T₁ and trailing edges of start pulses between the start and endof a period T₅;

FIG. 15 is a timing chart illustrating a case at the scan drivingcircuit according to the comparative example wherein a first start pulseand a second start pulse have been input to a first stage shift registerduring a period equivalent to one field period;

FIG. 16 is a circuit diagram of a scan driving circuit according to asecond embodiment;

FIG. 17 is a schematic timing chart of a shift register unit making upthe scan driving circuit shown in FIG. 16;

FIG. 18 is a schematic timing chart of an upstream stage of a logiccircuit unit making up the scan driving circuit shown in FIG. 16;

FIG. 19 is a schematic timing chart of a downstream stage of a logiccircuit unit making up the scan driving circuit shown in FIG. 16;

FIG. 20 is a circuit diagram of a driving circuit making up a displayelement at the m'th row and n'th column;

FIG. 21 is a circuit diagram of a scan driving circuit according to athird embodiment;

FIG. 22 is a schematic timing chart of a shift register unit making upthe scan driving circuit shown in FIG. 21;

FIG. 23 is a schematic timing chart of an upstream stage of a logiccircuit unit making up the scan driving circuit shown in FIG. 21;

FIG. 24 is a schematic timing chart of a downstream stage of a logiccircuit unit making up the scan driving circuit shown in FIG. 21;

FIG. 25 is a circuit diagram of a driving circuit making up a displayelement at the m'th row and n'th column;

FIG. 26 is an equivalent circuit diagram of a driving circuit making upa display element at the m'th row and n'th column in a display devicewhere display elements are arrayed in two-dimensional matrix fashion;

FIG. 27A is a schematic timing chart of signals on an initializationcontrol line, scanning line, and display control line;

FIG. 27B is a schematic diagram illustrating the on/off states of thetransistors of the driving circuit; and

FIGS. 28A and 28B are diagrams continuing from FIG. 27B, schematicallyillustrating the on/off states of the transistors in the drivingcircuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described with reference tothe drawings.

First Embodiment

The first embodiment relates to a scan driving circuit and to a displaydevice having the scan driving circuit. The display device according tothe first embodiment is a display device which uses display elementshaving a light emitting unit and a driving circuit thereof.

FIG. 1 is a circuit diagram of a scan driving circuit 110 according tothe first embodiment, FIG. 2 is a conceptual diagram of a display device1 according to the first embodiment, including the scan driving circuitshown in FIG. 1, FIG. 3 is a schematic timing chart of a shift registerunit 111 configuring the scan driving circuit 110 shown in FIG. 1, FIG.4 is a schematic timing chart of an upstream stage of a logic circuitunit 112 configuring the scan driving circuit 110 shown in FIG. 1, FIG.5 is a schematic timing chart of a downstream stage of the logic circuitunit 112 making up the scan driving circuit 110 shown in FIG. 1, andFIG. 6 is an equivalent circuit diagram of a driving circuit 11 makingup a display element 10 at the m'th (where m=1, 2, 3 . . . M) row andn'th (where n=1, 2, 3 . . . N) column of the display device shown inFIG. 2.

First, the overview of the display device 1 will be described. As shownin FIG. 2, the display device 1 includes:

(1) display elements 10 arrayed in the form of a two-dimensional matrix;

(2) scanning lines SCL, initialization control lines AZ configured toinitialize the display elements 10, and display control lines CLconfigured to control lit/unlit states of the display elements,extending in a first direction;

(3) data lines DTL extending in a second direction different from thefirst direction; and

(4) a scan driving circuit 110. The scanning lines SCL, initializationcontrol lines AZ, and display control lines CL are connected to the scandriving circuit 110. The data lines DTL are connected to a signal outputcircuit 100. Note that in FIG. 2, 3×3 display elements 10 are showncentered on a display element 10 at the m'th row and n'th column, butthis is only an exemplary illustration. Also, the power supply linesPS₁, PS₂, and PS₃, shown in FIG. 6, have been omitted from FIG. 2.

N display elements 10 are arrayed in the first direction and M arearrayed in the second direction which is different from the firstdirection. The display device 1 is configured of N/3×M pixels arrayed ona two-dimensional matrix form. One pixel is configured of threesub-pixels (a red light emitting sub-pixel which emits red light, agreen light emitting sub-pixel which emits green light, and a blue lightemitting sub-pixel which emits blue light). The display elements 10making up the pixels are driven in line sequence, at a display framerate of FR (times/second). That is to say, the display elements 10making up of each of the N/3 pixels arrayed at the m'th row (Nsub-pixels) are driven at the same time. In other words, the lit/unlittiming of the display elements 10 making up one row are subjected tocontrol in increments of the row to which they belong.

As shown in FIG. 6, a display element 10 is configured of a drivingcircuit 11 having a write transistor TR_(W), driving transistor TR_(D),and capacitance unit C₁, and a light emitting unit ELP to which currentis applied via the driving transistor TR_(D). The light emitting unitELP is configured of an electroluminescence light emitting unit. Thedisplay element 10 has a structure wherein the driving circuit 11 andthe light emitting unit ELP are layered. The driving circuit 11 furtherhas a first transistor TR₁, second transistor TR₂, third transistor TR₃,and fourth transistor TR₄; these transistors will be described later.

With the display element 10 at the m'th row and n'th column, onesource/drain region of the write transistor TR_(W) us connected to thedata line DTL_(n), and the gate electrode is connected to the scanningline SCL_(m). At the driving transistor TR_(D), one source/drain regionis connected to the other source/drain region of the write transistorTR_(W), thereby configuring a first node ND₁. One end of the capacitanceunit C₁ is connected to the power supply line PS₁. At the capacitanceunit C₁, a predetermined reference voltage (a later-describedpredetermined driving voltage V_(CC) in the first embodiment) is appliedto one end thereof, and the other end thereof is connected to the gateelectrode of the driving transistor TR_(D), thereby configuring a secondnode ND₂. The write transistor TR_(W) is controlled by signals from thescanning line SCL_(m).

Video signals (driving signals, luminance signals) V_(Sig) are appliedto the data line DTL_(n) from the signal output circuit 100 to controlluminance a the light emitting unit ELP, a point which will be describedlater.

The driving circuit 11 further has a first switch circuit unit SW₁connected between the second node ND₂ and the other source/drain regionof the driving transistor TR_(D). The first switch circuit unit SW₁ isconfigured of the first transistor TR₁. At the first transistor TR₁, onesource/drain region is connected to the second node ND₂, and the othersource/drain region is connected to the other source/drain region of thedriving transistor TR_(D). The gate electrode of the first transistorTR₁ is connected to the scanning line SCL_(m), and the first transistorTR₁ is controlled by signals from the scanning line SCL_(m).

The driving circuit 11 further has a second switch circuit unit SW₂connected between the second node ND₂ and the power supply line PS₃ towhich the later-described predetermined initialization voltage V_(Ini)is applied. The second switch circuit unit SW₂ is configured of thesecond transistor TR₂. At the second transistor TR₂, one source/drainregion is connected to the power supply line PS₃, and the othersource/drain region is connected to the second node ND₂. The gateelectrode of the second transistor TR₂ is connected to theinitialization control line AZ_(m), and the second transistor TR₂ iscontrolled by signals from the initialization control line AZ_(m).

The driving circuit 11 further has a third switch circuit unit SW₃connected between the first node ND₁ and the power supply line PS₁ towhich the driving voltage V_(CC) is applied. The third switch circuitunit SW₃ is configured of the third transistor TR₃. At the thirdtransistor TR₃, one source/drain region is connected to the power supplyline PS₁, and the other source/drain region is connected to the firstnode ND₁. The gate electrode of the third transistor TR₃ is connected tothe display control line CL_(m), and the third transistor TR₃ iscontrolled by signals from the display control line CL_(m).

The driving circuit 11 further has a fourth switch circuit unit SW₄connected between the other source/drain region of the drivingtransistor TR_(D) and one end of the light emitting unit ELP. The fourthswitch circuit unit SW₄ is configured of the fourth transistor TR₄. Atthe fourth transistor TR₄, one source/drain region is connected to othersource/drain region of the driving transistor TR_(D), and the othersource/drain region is connected to one end of the light emitting unitELP. The gate electrode of the fourth transistor TR₄ is connected to thedisplay control line CL_(m), and the fourth transistor TR₄ is controlledby signals from the display control line CL_(m). The other end of thelight emitting unit ELP (cathode electrode) is connected to the powersupply line PS₂, whereby a later-described voltage V_(Cat) is applied.The symbol C_(EL) represents the capacitance of the light emitting unitELP.

The driving transistor TR_(D) is configured of a p-channel type TFT, andthe write transistor TR_(W) also is configured of a p-channel type TFT.Further, the first transistor TR₁, second transistor TR₂, thirdtransistor TR₃, and fourth transistor TR₄ are also configured of ap-channel type TFTs. Note that the write transistor TR_(W) may beconfigured of an n-channel type TFT instead. The transistors aredescribed as being depression type transistors, but are not restrictedto this.

Widely-used configurations and structures may be used for theconfigurations and structures of the signal output circuit 100, scanninglines SCL, initialization control lines AZ, display control lines CL,and data lines DTL. The power supply lines PS₁, PS₂, and PS₃ extendingin the same first direction as the scanning lines SCL are connected toan unshown power source unit. The driving voltage V_(CC) is applied tothe power supply line PS₁, the voltage V_(Cat) is applied to the powersupply line PS₂, and the initialization voltage V_(Ini) is applied tothe power supply line PS₃. Widely-used configurations and structures maybe used for the configurations and structures of the power supply linesPS₁, PS₂, and PS₃ as well.

FIG. 7 is a partial cross-sectional diagram of a portion of a displayelement 10 making up the display device 1 shown in FIG. 2. Eachtransistor and the capacitance unit C₁ making up the driving circuit 11of the display element 10 are formed on a supporting body 20, and thelight emitting unit ELP is formed above the transistors and thecapacitance unit C₁ making up the driving circuit 11, with aninter-layer insulating layer 40 introduced therebetween, an arrangementwhich will be described later. The light emitting unit ELP has awidely-used configuration and structure of an anode electrode, holetransporting layer, emissive layer, electron transporting layer, cathodeelectrode, and so forth, for example. Note that in FIG. 7, only thedriving transistor TR_(D) is shown, and other transistors are hidden andare not visible. The other source/drain region of the driving transistorTR_(D) is electrically connected to an anode electrode provided to thelight emitting unit ELP via the unshown fourth transistor TR₄, theconnection between the fourth transistor TR₄ and the anode electrode ofthe light emitting unit ELP also not being visible.

The driving transistor TR_(D) is configured of a gate electrode 31, gateinsulating layer 32, and semiconductor layer 33. More specifically, thedriving transistor TR_(D) has a channel formation region 34corresponding to the semiconductor layer 33 between the one source/drainregion 35 and the other source/drain region 36 provided to thesemiconductor layer 33. The other unshown transistors are also ofsimilar configuration.

The capacitance unit C₁ is configured of an electrode 37, a dielectriclayer configured of an extended portion of the gate insulating layer 32,and an electrode 38. Note that the connection between the electrode 37and the gate electrode 31 of the driving transistor TR_(D), and theconnection between the electrode 38 and the power supply line PS₁, arenot visible.

The gate electrode 31, part of the gate insulating layer 32, and theelectrode 37 making up the capacitance unit C₁, are formed on thesupporting body 20. The driving transistor TR_(D) and capacitance unitC₁ and so forth are covered with the inter-layer insulating layer 40,with the light emitting unit ELP configured of an anode electrode 51,hole transporting layer, emissive layer, electron transporting layer,and cathode electrode 53 provided upon the inter-layer insulating layer40. Note that in FIG. 7, the hole transporting layer, emissive layer,and electron transporting layer are represented with a single layer 52.A second inter-layer insulating layer 54 is provided on the inter-layerinsulating layer 40 where the light emitting unit ELP is not provided, atransparent substrate 21 us disposed above the second inter-layerinsulating layer 54 and cathode electrode 53, and the light emitted atthe emissive layer is externally emitted through the substrate 21.Wiring 39 making up the cathode electrode 53 and power supply line PS₂is connected thereto via contact holes 56 and 55 provided in the secondinter-layer insulating layer 54 and inter-layer insulating layer 40,respectively.

A manufacturing method of the display device shown in FIG. 7 will bedescribed. First, the various types of wiring for the scanning lines andso forth, electrodes making up the capacitance units, transistors formedof semiconductor layers, inter-layer insulating layers, contact holes,and so forth, are formed on the supporting body 20 by techniques whichare widely employed. Next, film formation and patterning is performed bytechniques which are widely employed, thereby forming light emittingunits ELP arrayed in matrix fashion. The supporting body 20 which hasbeen subjected to the above processes is made to face a substrate 21 andthe perimeter thereof is sealed. This is then connected with the signaloutput circuit 100 and scan driving circuit 110, whereby a displaydevice can be completed.

Next, the scan driving circuit 110 will be described. Note thatdescription of the scan driving circuit 110 will be made with referenceto an arrangement wherein scanning signals for supply to scanning lineSCL₁ through scanning line SCL₃₁ in line sequence, to facilitatedescription. Description will be made in this way in other embodimentsas well.

As shown in FIG. 1, the scan driving circuit 110 includes:

(A) a shift register unit 111 configured of P (wherein P is a naturalnumber of 3 or greater, hereinafter the same) stages of shift registersSR, to sequentially shift input start pulses STP and output outputsignals ST from each stage; and

(B) a logic circuit unit 112 configured to operate based on outputsignals ST from the shift register unit 111, and enable signals (withthe first embodiment, later-described first enable signal EN₁ and secondenable signal EN₂).

With the output signals of a p'th (where p=1, 2, . . . P−1) stage shiftregister SR_(p) represented as ST_(p), the start of a start pulse of anoutput signal ST_(p+1) of a p+1'th shift register SR_(p+1) is situatedbetween the start and end of a start pulse of the output signal ST_(p),as shown in FIG. 3. The shift register unit 111 operates based on clocksignals CK and start pulses STP, so as to satisfy the above conditions.

The first stage shift register SR₁ receives input of a first start pulsethrough a U'th start pulse (wherein U is a natural number of 2 orgreater, hereinafter the same) within a period equivalent to one fieldperiod (in FIG. 3, a period equivalent from the start of period T₁through the end of period T₃₂. Note that in the first embodiment, U=2,and a first start pulse and a second start pulse are input.

Specifically, the first start pulse input to the first stage shiftregister SR₁ has the leading edge thereof between the start and end ofthe period T₁ shown in FIG. 3, and has the trailing edge thereof betweenthe start and end of the period T₁₃. Also, the second start pulse hasthe leading edge thereof between the start and end of the period T₁₇shown in FIG. 3 and has the trailing edge thereof between the start andend of the period T29. Each period such as T₁ in FIG. 3 and otherlater-described drawings correspond to one horizontal scanning period(also represented by “1H”). The clock signal CK is a square wave signalwhich inverts polarity every two horizontal scanning periods (2H).

The first start pulse in the output signal ST₁ of the shift register SR₁has the leading edge thereof at the start of the period T₃, and has thetrailing edge at the end of period T₁₄. The first pulse in the outputsignals ST₂, ST₃, and so on, for the shift register SR₂ and subsequentshift registers is a pulse which has been sequentially shifted by twohorizontal scanning periods. Also, second start pulse in the outputsignal ST₁ of the shift register SR₁ has the leading edge thereof at thestart of the period T₁₉, and has the trailing edge at the end of periodT₃₀. The first pulse in the output signals ST₂, ST₃, and so on, for theshift register SR₂ and subsequent shift registers is also a pulse whichhas been sequentially shifted by two horizontal scanning periods.

Also, one each of a first enable signal through a Q'th enable signal(where Q is a natural number of 2 or greater, hereinafter the same)exist in sequence between the start of the first start pulse of theoutput signal ST_(p) and the start of the first start pulse of theoutput signal ST_(p+1). In the first embodiment Q=2, and there are oneeach of the first enable signal EN₁ and the second enable signal EN₂, insequence. In other words, the first enable signal EN₁ and the secondenable signal EN₂ are signals generated so as to satisfy the aboveconditions, which basically are square wave signals of the same cyclebut with different phases. Note that one each of a first enable signalthrough a Q'th enable signal also exist in sequence between the start ofthe second start pulse of the output signal ST_(p) and the start of thesecond start pulse of the output signal ST_(p+1).

Specifically, the first enable signal EN₁ and the second enable signalEN₂ are square wave signals having two horizontal scanning periods asone cycle. In the first embodiment, these signals invert polarity everyhorizontal scanning period, and the first enable signal EN₁ and thesecond enable signal EN₂ are in inverse phase relation. While FIGS. 3through 5 show the high level of the enable signals EN₁ and EN₂ aslasting for one horizontal scanning period, the present invention is notrestricted to this arrangement, and the high level may be a square wavesignal with a period shorter than one horizontal scanning period, apoint which holds true with the other embodiments as well.

For example, there sequentially exist one each of the first enablesignal EN₁ in the period T₃ and the second enable signal EN₂ in theperiod T₄, between the start of the start pulse in output signal ST₁(i.e., the start of period T₃) and the start of the start pulse inoutput signal ST₂ (i.e., the start of period T₃). In the same way, theresequentially exist one each of the first enable signal EN₁ and thesecond enable signal EN₂, between the start of the start pulse in outputsignal ST₂ and the start of the start pulse in output signal ST₃. Thisis the same for output signal ST₄ and on.

As shown in FIG. 1, the logic circuit unit 112 has (P−2)×Q NAND circuits113. Specifically, the logic circuit unit 112 has (1, 1)'th through(P−2, 2)'th NAND circuits 113. Period identifying signals SP foridentifying each period from the start of the u'th start pulse (whereu=1, 2, . . . U−1, hereinafter the same) start pulse in an output signalST₁ to the start of a (u+1)'th start pulse, and a period from the startof the U'th start pulse to the start of the first start pulse in thenext frame, are input to the logic circuit unit 112.

In the first embodiment, U=2, and the period identifying signal SP is asignal for identifying the period from the start of the first startpulse in the output signal ST₁ to the start of the second start pulse,and the period from the start of the second start pulse in output signalST₁ to the start of the first start pulse in the next frame. In FIGS. 3through 5, the period from the start of the first start pulse in theoutput signal ST₁ to the start of the second start pulse is a periodfrom the start of period T₃ to the end of period T₁₈. Also, the periodfrom the start of the second start pulse in output signal ST₁ to thestart of the first start pulse in the next frame is a period from thestart of period T₁₉ to the end of period T₂ in the next frame. In thefirst embodiment, the period identifying signal SP is a signal which isat high level during the period from the start of period T₃ to the endof period T₁₈, and at low level during the period from the start ofperiod T₁₉ to the end of period T₂ of the next frame.

With a q'th enable signal (where q is an arbitrary number from 1 to Q,hereinafter the same) represented as EN_(q), a signal based on theperiod identifying signal SP, the output signal ST_(p), a signalobtained by inverting the output signal ST_(p+1), and the q'th enablesignal EN_(q), are input to a (p′, q)'th NAND circuit 113 (where p is anarbitrary natural number from 1 to (P−2), hereinafter the same). Asdescribed later, the operations of the NAND circuit 113 are restrictedbased on the period identifying signal SP, such that the NAND circuit113 generates scanning signals based only on a portion of the outputsignal ST_(p′) corresponding to the first start pulse, the signalobtained by inverting the output signal ST_(p′+1), and the q'th enablesignal EN_(q).

More specifically, the output signal ST_(p′+1) is inverted by the NORcircuit 114 shown in FIG. 1, and input to the input side of the (p′,q)'th NAND circuit 113. The output signal ST_(p′) and the q'th enablesignal EN_(q) are directly input to the input side of the (p′, q)'thNAND circuit 113. Also, the period identifying signal SP is directlyinput to the input side of the (1, 1)'th through (8, 2)'th NAND circuits113, as a signal based on the period identifying signal SP. the periodidentifying signal SP inverted by a NOR circuit 116 shown in FIG. 1 isinput to the input side of the (9, 1)'th and subsequent NAND circuits113, as a signal based on the period identifying signal SP.

As described above, the first start pulse and second start pulse areinput to the first stage shift register SR₁ within a period equivalentto one field period. If the (p′, q)'th NAND circuit 113 were to operateonly by the output signal ST_(p′), a signal obtained by inverting theoutput signal ST_(p′+1), and the q'th enable signal EN_(q), the NANDcircuit 113 would generate two scanning signals in the one field period.This will be described in detail next.

Let us consider the (8, 1)'th NAND circuit 113. Signals based on thescanning signals from the (8, 1)'th NAND circuit 113 are supplied to thescanning line SCL₁₄. As shown in FIG. 4, in the period T₁₇ in which thescanning signal should be generated, the output signal ST₈, the signalobtained by inverting the output signal ST₉, and the first enable signalEN₁, are at high level. However, the first stage shift register SR₁ hasalso received input of the second start pulse in addition to the firststart pulse, so the output signal ST₈, the signal obtained by invertingthe output signal ST₉, and the first enable signal EN₁, are at highlevel in period T₁ as well.

Accordingly, if the (8, 1)'th NAND circuit 113 were to operate basedonly on the output signal ST₈, a signal obtained by inverting the outputsignal ST₉, and the first enable signal EN₁, trouble would occur in thata scanning signal would be supplied to the scanning line SCL₁₄ not onlyin the period T₁₇ in which the scanning signal should be generated, butalso in the period T₁.

In the first embodiment, the operations of the NAND circuit 113 arerestricted based on the period identifying signal SP, so trouble where ascanning signal is supplied in the period T₁ does not occur. That is tosay, the period identifying signal SP is directly input to the inputside of the (8, 1)'th NAND circuit 113, as a signal based on the periodidentifying signal SP, as described above. In period T₁, the periodidentifying signal SP is at a low level. Accordingly, in period T₁ theoperations of the NAND circuit 113 are restricted, and do not generate ascanning signal. On the other hand, in period T₁₇, the periodidentifying signal SP is at a high level. Accordingly, the (8, 1)'thNAND circuit 113 generates a scanning signal based only on a portion ofthe output signal ST₈ corresponding to the first start pulse, a signalobtained by inverting the output signal ST₉, and the first enable signalEN₁.

Let us also consider the (9, 1)'th NAND circuit 113. Signals based onthe scanning signals from the (9, 1)'th NAND circuit 113 are supplied tothe scanning line SCL₁₆ shown in FIG. 1. A signal based on the periodidentifying signal SP, the output signal ST₉, the signal obtained byinverting the output signal ST₁₀, and the first enable signal EN₁, areapplied to the input side of the (9, 1)'th NAND circuit 113. Unlike thecase of the (8, 1)'th NAND circuit 113, a period identifying signal SPinverted by the NOR circuit 116 is input to the input side of the (9,1)'th NAND circuit 113 as a signal based on the period identifyingsignal SP.

As shown in FIG. 5, in the period T₁₉ in which the scanning signalshould be generated, the output signal ST₉, the signal obtained byinverting the output signal ST₁₀, and the first enable signal EN₁, areat high level. However, the first stage shift register SR₁ has alsoreceived input of the second start pulse in addition to the first startpulse, so the output signal ST₉, the signal obtained by inverting theoutput signal ST₁₀, and the first enable signal EN₁, are at high levelin period T₃ as well. As described above, a period identifying signal SPinverted by the NOR circuit 116 is input to the input side of the (9,1)'th NAND circuit 113. In period T₃, the period identifying signal SPis at a high level, so in period T₃ the (9, 1)'th NAND circuit 113 doesnot generate a scanning signal. On the other hand, in period T₁₉, theperiod identifying signal SP is at a low level, so the (9, 1)'th NANDcircuit 113 generates a scanning signal in period T₁₉.

While description has been made regarding the operations of the (8,1)'th NAND circuit 113 and the (9, 1)'th NAND circuit 113, theoperations are the same for the other NAND circuits 113 as well. The(p′, q)'th NAND circuit 113 generates a scanning signal based only on aportion of the output signal ST_(p) corresponding to the first startpulse, the signal obtained by inverting the output signal ST_(p′+1), andthe q'th enable signal EN_(q).

Description of the display device 1 will continue. As shown in FIG. 1,signals of the (1, 2)'th NAND circuit 113 are supplied to the scanningline SCL₁ connected to the first row of display elements 10, and signalsof the (2, 1)'th NAND circuit 113 are supplied to the scanning line SCL₂connected to the second row of display elements 10. This is true for theother scanning line SCL as well. That is to say, signals of the (p′,q)'th NAND circuit 113 (excluding a case wherein p′=1 and q=1) aresupplied to the scanning line SCL_(m) connected to the m'th (wherem=Q×(p′−1)+q−1) row of display elements 10.

The display elements 10 to which signals based on the scanning signalsfrom the (p′, q)'th NAND circuit 113 are supplied via the scanning lineSCL_(m) are supplied with signals based on scanning signals from the(p′−1, q′)'th NAND circuit 113 (where q′ is a natural number from 1through Q, hereinafter the same) in the event that q=1, and signalsbased on scanning signals from the (p′, q″)'th NAND circuit 113 (whereq″ is a natural number from 1 through (q−1), hereinafter the same) inthe event that q>1, via the initialization control line AZ_(m) connectedto the display elements 10.

More specifically, in the first embodiment, the display elements 10 towhich signals based on the scanning signals from the (p′, q)'th NANDcircuit 113 are supplied via the scanning line SCL_(m), are suppliedwith signals based on scanning signals from the (p′−1, Q)'th NANDcircuit 113 in the event that q=1, and signals based on scanning signalsfrom the (p′, q−1)'th NAND circuit 113 in the event that q>1, via theinitialization control line AZ_(m) connected to the display elements 10.

Also, the display control line CL_(m) connected to the display elements10 is supplied with signals based on the output signal ST_(p′+1) fromthe (p′+1)'th stage shift register SR_(p′+1) in the case that q=1, andis supplied with signals based on the output signal ST_(p′+2) from the(p′+2)'th stage shift register SR_(p′+2) in the case that q>1. Note thatthe third transistor TR₃ and fourth transistor TR₄ shown in FIG. 6 arep-channel type transistors, so signals are supplied to the displaycontrol line CL_(m) via the NOR circuit 115.

Description will be made in further detail with reference to FIG. 1. Forexample, looking at the display elements 10 to which signals based onthe scanning signals from the (8′, 1)'th NAND circuit 113 are suppliedvia the scanning line SCL₁₄, the initialization control line AZ₁₄connected to the display element 10 is supplied with signals based onthe scanning signals from the (7′, 2)'th NAND circuit 113. Signals basedon the output signal ST₉ from the ninth stage shift register SR₉ aresupplied to the display control line CL₁₄ connected to the displayelement 10. Also, looking at the display elements 10 to which signalsbased on the scanning signals from the (8′, 2)'th NAND circuit 113 aresupplied via the scanning line SCL₁₅, the initialization control lineAZ₁₅ connected to the display element 10 is supplied with signals basedon the scanning signals from the (8′, 1)'th NAND circuit 113. Signalsbased on the output signal ST₁₀ from the tenth stage shift register SR₁₀are supplied to the display control line CL₁₅ connected to the displayelement 10.

Next, operation of the display device 1 will be described regardingoperations of a display element 10 at the m'th row and n'th column, towhich signals of the (p′, q)'th NAND circuit 113 are supplied from thescanning line SCL_(m). This display element 10 will hereinafter bereferred to as “(n, m)'th display element 10” or “(n, m)'th sub-pixel”.Also, the horizontal scanning period of the display elements 10 arrayedon the m'th row (more specifically, the m'th horizontal scanning periodof the current display frame) will be referred to simply as “m'thhorizontal scanning period”. This will be the same for the otherembodiments described later, as well.

FIG. 8 is a schematic driving timing chart of the display element 10 atthe m'th row and n'th column. Also, FIGS. 9A and 9B are diagramsschematically illustrating the on/off states of the transistors in thedriving circuit 11 making up the display element 10 at the m'th row andn'th column. FIGS. 10A and 10B are diagrams continuing from FIGS. 9A and9B, schematically illustrating the on/off states of the transistors inthe driving circuit 11 making up the display element 10 at the m'th rowand n'th column. FIGS. 11A and 11B are diagrams continuing from FIGS.10A and 10B, schematically illustrating the on/off states of thetransistors in the driving circuit 11 making up the display element 10at the m'th row and n'th column. FIGS. 12A and 12B are diagramscontinuing from FIGS. 11A and 11B, schematically illustrating the on/offstates of the transistors in the driving circuit 11 making up thedisplay element 10 at the m'th row and n'th column.

Note that, for the sake of facilitating description, p′=8 and q=1, andm=14, when comparing the timing chart in FIG. 8 with FIGS. 3 through 5.Specifically, the timing chart of initialization control line AZ₁₄,scanning line SCL₁₄, and display control line CL₁₄ in FIG. 4 is to bereferred to.

In the lit state of the display element 10, the driving transistorTR_(D) is driven so as to apply drain current I_(ds) in accordance withthe following Expression (1). In the lit state of the display element10, the one source/drain region of the driving transistor TR_(D) acts asa source region, and the other source/drain region acts as a drainregion. To facilitate description, in the following description, the onesource/drain region of the driving transistor TR_(D) may be referred tosimply as “source region”, and the other source/drain region simply as“drain region”. We will also say that

-   μ effective mobility,-   L channel length,-   W channel width,-   V_(gs) voltage difference between the source region and gate region,    and-   C_(OX) (relative permittivity of gate insulation    layer)×(permittivity of vacuum)/(thickness of gate insulation    layer).    I _(ds) =k·μ·(V _(gs) −V _(th))²  (1)

Also, while the following voltage and potential values will be used inthe first embodiment and later-described other embodiments, these areonly values for explanatory purposes, and the present invention is notrestricted to these values.

-   V_(Sig) Video signal for controlling the luminance at the light    emitting unit ELP

0 volts (maximum luminance) to 8 volts (minimum luminance)

-   V_(CC) Driving voltage

10 volts

-   V_(Ini) Initialization voltage for initializing the potential of the    second node ND₂

−4 volts

-   V_(th) Threshold voltage of driving transistor TR_(D)

2 volts

-   V_(Cat) Voltage applied to power supply line PS₂

−10 volts

Period TP(1)⁻² (See FIGS. 8A through 9A)

The Period TP(1)⁻² is a period in which the (n, m)'th display element 10is in a lit state, in accordance with the video signal V′_(Sig) writtenthereto earlier. For example, in the case of m=14, the Period TP(1)⁻²corresponds to the period from the start of the period T′₃ (periodcorresponding to period T₃ shown in FIG. 4 in the preceding frame) tothe end of the period T₁₄. The initialization control line AZ₁₄ andscanning line SCL₁₄ are at the high level, and the display control lineCL₁₄ is at the low level.

Accordingly, the write transistor TR_(W), first transistor TR₁, andsecond transistor TR₂ are in an off state. The third transistor TR₃ andfourth transistor TR₄ are in an on state. The light emitting unit ELP atthe display element 10 making up the (n, m)'th display element 10 hasapplied thereto a drain current I′_(ds) based on a later-describedExpression (5), and the luminance of the display element 10 configuringthe (n, m)'th sub-pixels is a value corresponding to this drain currentI′_(ds).

Period TP(1)⁻¹ (See FIGS. 8A, 8B, and 9B)

The (n, m)'th display element 10 is in an unlit state from this PeriodTP(1)⁻¹ is to a later-described Period TP(1)₂. For example, in the caseof m=14, the Period TP(1)⁻¹ corresponds to the period T′₁₅ in FIG. 4.The initialization control line AZ₁₄ and scanning line SCL₁₄ maintainthe high level, and the display control line CL₁₄ goes to the highlevel.

Accordingly, the write transistor TR_(W), first transistor TR₁, andsecond transistor TR₂ maintain the off state. The third transistor TR₃and fourth transistor TR₄ go from the on state to the off state. Thus,the first node ND₁ is in a state of being cut off from the power supplyline PS₁, and further, the light emitting unit ELP and drivingtransistor TR_(D) are in a state of being cut off. Accordingly, currentdoes not flow to the light emitting unit ELP, which is accordingly in anoff state.

Period TP(1)₀ (See FIGS. 8A, 8B, and 10A)

The Period TP(1)₀ is the (m−1)'th horizontal scanning period in thecurrent display frame. For example, in the case of m=14, the PeriodTP(1)₀ corresponds to the period T₁₆ in FIG. 4. The scanning line SCL₁₄and the display control line CL₁₄ maintain the high level. Theinitialization control line AZ₁₄ goes to the low level, and then goes tothe high level at the end of the period T₁₆.

In this Period TP(1)₀, the first switch circuit unit SW₁, third switchcircuit unit SW₃, and fourth switch circuit unit SW₄ maintain the offstate, and following applying the predetermined initialization voltageV_(Ini) from the power supply line PS₃ to the second node ND₂ via thesecond switch circuit unit SW₂ placed in the on state, the second switchcircuit unit SW₂ is set to an off state, thereby performing aninitialization process for setting the potential of the second node ND₂to the predetermined reference potential.

That is to say, the write transistor TR_(W), first transistor TR₁, thirdtransistor TR₃, and fourth transistor TR₄ are in an off state. Thesecond transistor TR₂ goes from an off state to an on state, and thepredetermined initialization voltage V_(Ini) is applied from the powersupply line PS₃ via the second transistor TR₂ placed in the on state. Atthe end of the Period TP(1)₀, the second transistor TR₂ goes to the offstate. The driving voltage V_(CC) is applied to one end of thecapacitance unit C₁ such that the potential at the one end of thecapacitance unit C₁ is in a maintained state, so the potential of thesecond node ND₂ is set to the predetermined reference voltage (−4 volts)by the initialization voltage V_(Ini).

Period TP(1)₁ (See FIGS. 8A, 8B, and 10B)

The Period TP(1)₁ is the m'th horizontal scanning period in the currentdisplay frame. For example, in the case of m=14, the Period TP(1)₁corresponds to the period T₁₇ in FIG. 4. The initialization control lineAZ₁₄ and the display control line CL₁₄ are at the high level, and thescanning line SCL₁₄ goes to the low level.

In this Period TP(1)₁, the second switch circuit unit SW₂, third switchcircuit unit SW₃, and fourth switch circuit unit SW₄ maintain the offstate, the first switch circuit unit SW₁ is placed in an on state, andin a state wherein the second node ND₂ and the other source/drain regionof the driving transistor TR_(D) are electrically connected by the firstswitch circuit unit SW₁ in the on state, the video signal V_(Sig) isapplied from the data line DTL_(n) to the first node ND₁ via the writetransistor TR_(W) placed in the on state by the signals from thescanning line SCL_(m), thereby performing a writing process for changingthe potential of the second node ND₂ toward a potential which can becalculated by subtracting the threshold voltage V_(th) of the drivingtransistor TR_(D) from the video signal V_(Sig).

That is to say, the off state of the second transistor TR₂, thirdtransistor TR₃, and fourth transistor TR₄ is maintained. The writetransistor TR_(W) and first transistor TR₁ are placed in an one state bysignals from the scanning line SCL_(m). The second node ND₂ and theother source/drain region of the driving transistor TR_(D) are placed inan electrically connected state via the first transistor TR₁ in the onstate. Also, the video signal V_(Sig) is applied from the data lineDTL_(n) to the first node ND₁ via the write transistor TR_(W) which hasbeen placed in the on state by the signal from the scanning lineSCL_(m). Accordingly, the potential of the second node ND₂ changestoward a potential which can be calculated by subtracting the thresholdvoltage V_(th) of the driving transistor TR_(D) from the video signalV_(Sig).

That is to say, due to the above-described initialization process, thepotential of the second node ND₂ is initialized such that the drivingtransistor TR_(D) is in an on state at the start of the Period TP(1)₁,so the potential of the second node ND₂ changes toward the potential ofthe video signal V_(Sig) applied to the first node ND₁. However, uponthe potential difference between the gate electrode of the drivingtransistor TR_(D) and the one source/drain region reaching the thresholdvoltage V_(th), the driving transistor TR_(D) goes to an off state. Inthis state, the potential of the second node ND₂ is approximately(V_(Sig)−V_(th)). The voltage V_(ND2) of the second node ND₂ is asexpressed in the following Expression (2). Before the (m+1)'thhorizontal scanning period starts, the write transistor TR_(W) and firsttransistor TR₁ are placed in an off state by signals from the scanningline SCL_(m).V _(ND2)≈(V _(Sig) −V _(th))  (2)Period TP(1)₂ (See FIGS. 8A, 8B, 11A)

The Period TP(1)₂ is a period up to the emitting period startingfollowing the writing process, and the (n, m)'th display element 10 isin an unlit state. For example, in the case of m=14, the Period TP(1)₂corresponds to the period T₁₈ in FIG. 4. The scanning line SCL₁₄ goes tothe high level, and the initialization control line AZ₁₄ and displaycontrol line CL₁₄ maintain the high level.

Accordingly, the write transistor TR_(W) and first transistor TR₁ go toan off state, and the second transistor TR₂, third transistor TR₃, andfourth transistor TR₄ maintain the off state. The first node ND₁maintains the state of being cut off from the power supply line PS₁, andthe light emitting unit ELP and driving transistor TR_(D) maintain thestate of being cut off. The potential V_(ND2) of the second node ND₂maintains the above Expression (2) due to the capacitance unit C₁.

Period TP(1)₃ (See FIGS. 8A, 8B, 11B)

In this Period TP(1)₃, the first switch circuit unit SW₁ and secondswitch circuit unit SW₂ maintain the off state, the other source/drainregion of the driving transistor TR_(D) and the one end of the lightemitting unit ELP are electrically connected via the fourth switchcircuit unit SW₄ placed in an on state, the predetermined drivingvoltage V_(CC) is applied to the first node ND₁ from the power supplyline PS₁ via the third switch circuit unit SW₃ placed on the on state,thereby performing an emitting process for driving the light emittingunit ELP by applying current to the light emitting unit ELP via thedriving transistor TR_(D).

For example, in the case of m=14, the Period TP(1)₃ corresponds to theperiod from the start of period T₁₉ to the end of period T₃₀ in FIG. 4.The initialization control line AZ₁₄ and scanning line SCL₁₄ maintainthe high level and the display control line CL₁₄ goes to the low level.

That is to say, the first transistor TR₁ and second transistor TR₂maintain the off state, and the third transistor TR₃ and fourthtransistor TR₄ go from the off state to the on state due to signals fromthe display control line CL_(m). The predetermined driving voltageV_(CC) is applied to the first node ND₁ via the third transistor TR₃placed in the on state. Also, the other source/drain region of thedriving transistor TR_(D) and the one end of the light emitting unit ELPare electrically connected via the fourth transistor TR₄ which has beenplaced in the on state. Thus, the light emitting unit ELP is driven bycurrent being applied to the light emitting unit ELP via the drivingtransistor TR_(D).

Based on Expression (2),V _(gs) ≈V _(CC)−(V _(Sig) −V _(th))holds, so Expression (1) can be rewritten as follows.

$\begin{matrix}\begin{matrix}{I_{ds} = {k \cdot \mu \cdot \left( {V_{gs} - V_{th}} \right)^{2}}} \\{= {k \cdot \mu \cdot \left( {V_{CC} - V_{Sig}} \right)^{2}}}\end{matrix} & (4)\end{matrix}$

Accordingly, the current I_(ds) of the light emitting unit ELP isproportionate to the value of the potential difference between V_(CC)and V_(Sig) squared. In other words, the current I_(ds) flowing throughthe light emitting unit ELP is not dependent on the threshold voltageV_(th) of the driving transistor TR_(D), meaning that the amount ofemission (luminance) of the light emitting unit ELP is not affected bythe threshold voltage V_(th) of the driving transistor TR_(D). Theluminance of the (n, m)'th display element 10 is a value correspondingto this I_(ds).

Period TP(1)₄ (See FIGS. 8A, 8B, 12A)

In the case of m=14 for example, this Period TP(1)₄ is the periodbetween the end of the second start pulse in the output signal ST₉ (theend of the period T₃₀ in FIG. 4) and immediately before the leading edgeof the first start pulse in the next frame (the end of the period T₂ inthe next frame in FIG. 4). At the start of this period, the outputsignal ST₉ goes from the high level to the low level. The displaycontrol line CL₈ goes from the low level to the high level. Theinitialization control line AZ₈ and scanning line SCL₈ maintain the highlevel.

Accordingly, the third transistor TR₃ and fourth transistor TR₄ go fromthe on state to the off state. The write transistor TR_(W), firsttransistor TR₁, and second transistor TR₂ maintain the off state.Accordingly, the first node ND₁ is cut off from the power supply linePS₁, and further, the light emitting unit ELP and driving transistorTR_(D) are in a cut off state. Thus, no current flows to the lightemitting unit ELP, which is accordingly in an unlit state.

Period TP(1)₅ (See FIGS. 8A, 8B, 12B)

In the case of m=14 for example, this Period TP(1)₅ is the period afterthe start of the first start pulse in the next frame (the start of theperiod T₃ in the next frame in FIG. 4). In this period, the outputsignal ST₉ goes from the low level to the high level. The displaycontrol line CL₈ goes from the high level to the low level. Theinitialization control line AZ₈ and scanning line SCL₈ maintain the highlevel.

Accordingly, the third transistor TR₃ and fourth transistor TR₄ go fromthe off state to the on state. The write transistor TR_(W), firsttransistor TR₁, and second transistor TR₂ maintain the off state.Accordingly, the first node ND₁ and the power supply line PS₁ arereconnected, and the light emitting unit ELP and driving transistorTR_(D) are also reconnected. Thus, current flows to the light emittingunit ELP, which is accordingly in lit state again.

The lit state of the light emitting unit ELP continues to a periodequivalent to the end of the Period TP(1)⁻² of the next frame. Thus, theoperations of emission of the display element 10 configuring the (n,m)'th sub-pixels are completed.

The length of the until period is the same, regardless of the value ofm. However, the ratio of the Period TP(1)⁻¹ and Period TP(1)₂ making upthe unlit periods change depending on the value of m. This holds true inthe later-described other embodiments as well. For example, in thetiming chart for scanning line SCL₁₅ in FIG. 4, there is no PeriodTP(1)⁻¹. Note that the absence of the Period TP(1)⁻¹ does not pose anyproblem in particular to operations of the display device.

The scan driving circuit 110 according to the first example is anintegrated circuit of a structure where signals are supplied to thescanning lines SCL, initialization control line AZ, and display controlline CL. Accordingly, reduction in layout area of the circuits, andreduction of circuit costs can be realized. Also, with the displaydevice 1 according to the first embodiment, the lit/unlit state of thedisplay elements 10 can be switched multiple times in one field periodby a simple arrangement of changing the number of start pulses input tothe first stage shift register making up the scan driving circuit 110,thereby reducing flickering of the image displayed on the displaydevice.

Description will further be made with comparison to a comparativeexample. FIG. 13 is a circuit diagram of a scan driving circuit 120according to a comparative example. In the scan driving circuit 120, theconfiguration of a logic circuit unit 122 differs from the logic circuitunit 112 of the scan driving circuit 110 according to the firstembodiment. The configuration of the shift register unit 121 of the scandriving circuit 120 is the same as the shift register unit 111 of thescan driving circuit 110.

More specifically, with the scan driving circuit 120, the periodidentifying signal SP has been omitted, and further, the NOR circuits114 and 115 shown in FIG. 1 have been omitted. Also, at the displayelement 10 to which signals based on scanning signals from a (p′, q)'thNAND circuit 123 are supplied via the scanning line SCL, signals basedon the output signal ST_(p′) from the (p′)'th shift register SR_(p′) aresupplied in the case of q=1, and signals based on the output signalST_(p′+1) from the p′+1'th shift register SR_(p′+1) are supplied in thecase of q>1, from the display control line CL connected to the displayelement 10.

With the scan driving circuit 120 of the configuration described above,the (p′, q)'th NAND circuit 123 generates scanning signals based on theoutput signal ST_(p), output signal ST_(p′+1), and the q'th enablesignal EN_(q). Accordingly, in the event that there are multiple q'thenable signals EN_(q) in the overlapping period of the start pulse ofoutput signal ST_(p′) and the start pulse of output signal ST_(p′+1),multiple scan signals will be generated in the overlapping period.Accordingly, if the start pulse STP is to have a leading edge betweenthe start of the period T₁ and the end thereof, settings have to be madesuch that the trailing edge of the start pulse SR_(p) is between thestart and end of the period T₅. The scan driving circuit 110 accordingto the first embodiment does not have such restrictions.

FIG. 14 is a timing chart of the scan driving circuit 120 shown in FIG.13 where the start pulse STP has a leading edge between the start andend of the period T₁, and a trailing edge between the start and end ofthe period T₅. As can be clearly seen in comparison with the timingchart in FIG. 4, similar signals as with the case in FIG. 4 are suppliedto the initialization control line AZ and scanning line SCL, albeitthere be phase shifting.

FIG. 15 is a timing chart regarding the scan driving circuit 120according to the comparative example, where the first start pulse andsecond start pulse are input to the first stage shift register SR₁within a period equivalent to one field period. In this case, multiplescanning signals are generated within one field period. Accordingly,with the scan driving circuit 120 according to the comparative example,there are restrictions that only one start pulse can be input to thefirst stage shift register SR₁, and also there are restrictionsregarding the end thereof, as well. The scan driving circuit 110according to the first embodiment has no such restrictions.

Second Embodiment

The second embodiment also relates to a scan driving circuit and to adisplay device having the scan driving circuit. As shown in FIG. 2, thedisplay device 2 is of the same configuration as the display device 1according to the first embodiment, other than the scan driving circuitbeing different. Accordingly, description of the display device 2according to the second embodiment will be omitted.

FIG. 16 is a circuit diagram of a scan driving circuit according to asecond embodiment, FIG. 17 is a schematic timing chart of a shiftregister unit making up the scan driving circuit shown in FIG. 16, FIG.18 is a schematic timing chart of an upstream stage of a logic circuitunit 212 making up the scan driving circuit 210 shown in FIG. 16, andFIG. 19 is a schematic timing chart of a downstream stage of a logiccircuit unit 212 making up the scan driving circuit 210 shown in FIG.16.

With the scan driving circuit 110 according to the first embodiment, thefirst start pulse and second start pulse are input to the first stageshift register SR₁ in a period equivalent to one field period. With thescan driving circuit 210 according to the second embodiment, a thirdstart pulse and fourth start pulse are also input in addition to these.Also, with the second embodiment, the period identifying signal isconfigured of a first period identifying signal SP₁ and a second periodidentifying signal SP₂. These are the primary points in which the secondembodiment differs from the first embodiment. With the secondembodiment, four periods are identified by combining the high/low levelof the first period identifying signal SP₁ and second period identifyingsignal SP₂. Accordingly, with the second embodiment, the number of timesof switching the display elements between lit/unlit states can beincreased beyond that of the first embodiment.

As shown in FIG. 16, the scan driving circuit 210 also includes:

(A) a shift register unit 211 configured of P stages of shift registersSR, to sequentially shift input start pulses STP and output outputsignals ST from each stage; and

(B) a logic circuit unit 212 configured to operate based on outputsignals ST from the shift register unit 211, and enable signals (as withthe first embodiment, first enable signal EN₁ and second enable signalEN₂).

With the scan driving circuit 210, the configuration of the logiccircuit unit 212 differs from that of the logic circuit unit 112 of thescan driving circuit 110 according to the first embodiment. Theconfiguration of the shift register unit 211 of the scan driving circuit210 is the same as that of the shift register unit 111 of the scandriving circuit 110.

As mentioned above, the first start pulse through fourth start pulse areinput to the first stage shift register SR₁ within a period equivalentto one field period. Specifically, as shown in FIG. 17, the first startpulse input to the first stage shift register SR₁ is a pulse having aleading edge between the start and of the period T₁ and having atrailing edge between the start and of the period T₅. The second startpulse is a pulse having a leading edge between the start and of theperiod T₉ and having a trailing edge between the start and of the periodT₁₃. The third start pulse is a pulse having a leading edge between thestart and of the period T₁₇ and having a trailing edge between the startand of the period T₂₁. The fourth start pulse is a pulse having aleading edge between the start and of the period T₂₅ and having atrailing edge between the start and of the period T₂₉.

As with the case of the first embodiment, the clock signal CK is asquare wave signal which inverts polarity every two horizontal scanningperiods (2H). The first start pulse in the output signal ST₁ of theshift register SR₁ has the leading edge thereof at the start of theperiod T₃, and has the trailing edge at the end of period T₆. The firststart pulse in the output signals ST₂, ST₃, and so on, for the shiftregister SR₂ and subsequent shift registers is a pulse which has beensequentially shifted by two horizontal scanning periods.

Also, the second start pulse in the output signal ST₁ of the shiftregister SR₁ has the leading edge thereof at the start of the periodT₁₁, and has the trailing edge at the end of period T₁₄. The third startpulse in the output signal ST₁ of the shift register SR₁ has the leadingedge thereof at the start of the period T₁₉, and has the trailing edgeat the end of period T₂₂. The fourth start pulse in the output signalST₁ of the shift register SR₁ has the leading edge thereof at the startof the period T₂₇, and has the trailing edge at the end of period T₃₀.The second through fourth pulses in the output signals ST₂, ST₃, and soon, for the shift register SR₂ and subsequent shift registers, are alsopulses which have been sequentially shifted by two horizontal scanningperiods.

Also, one each of a first enable signal through a Q'th enable signalexist in sequence between the start of the first start pulse of theoutput signal ST_(p) and the start of the first start pulse of theoutput signal ST_(p+1). In the second embodiment as well, Q=2, and thereare one each of the first enable signal EN₁ and the second enable signalEN₂, in sequence. The first enable signal EN₁ and the second enablesignal EN₂ have been described in the first embodiment, and accordinglydescription thereof will be omitted here.

As shown in FIG. 16, the logic circuit unit 212 has (P−2)×Q NANDcircuits 213. Specifically, the logic circuit unit 212 has (1, 1)'ththrough (P−2, 2)'th NAND circuits 213. Period identifying signals SP foridentifying each period from the start of the u'th start pulse startpulse in an output signal ST₁ to the start of a (u+1)'th start pulse,and a period from the start of the U'th start pulse to the start of thefirst start pulse in the next frame, are input to the logic circuit unit212.

In the second embodiment, U=4, and the period identifying signal SP is asignal for identifying the period from the start of the first startpulse in the output signal ST₁ to the start of the second start pulse,the period from the start of the second start pulse to the start of thethird start pulse, the period from the start of the third start pulse tothe start of the fourth start pulse, and the period from the start ofthe fourth start pulse to the start of the first start pulse in the nextframe. In the second embodiment, the period identifying signal SP isconfigured of the first period identifying signal SP₁ and the secondperiod identifying signal SP₂.

The first period identifying signal SP₁ is a signal which is at highlevel during the period from the start of period T₃ to the end of periodT₁₈, and at low level during the period from the start of period T₁₉ tothe end of period T₂ of the next frame. That is to say, the first periodidentifying signal SP₁ is the same as the period identifying signal SPin the first embodiment. Conversely, the second period identifyingsignal SP₂ is a signal which is at high level during the period from thestart of period T₃ to the end of period T₁₀, at low level during theperiod from the start of period T₁₁ to the end of period T₁₈, at highlevel during the period from the start of period T₁₉ to the end ofperiod T₂₆, and at low level during the period from the start of periodT₂₇ to the end of period T₂ of the next frame.

With a q'th enable signal represented as EN_(q), as shown in FIG. 16signals based on the period identifying signal SP (i.e., a signal basedon the first period identifying signal SP₁ and a signal based on thesecond period identifying signal SP₂), the output signal ST_(p), asignal obtained by inverting the output signal ST_(p+1), and the q'thenable signal EN_(q), are input to a (p′, q)'th NAND circuit 213,whereby the operations of the NAND circuit 213 are restricted based onthe first period identifying signal SP₁ and second period identifyingsignal SP₂, such that the NAND circuit 213 generates scanning signalsbased only on a portion of the output signal ST_(p′) corresponding tothe first start pulse, the signal obtained by inverting the outputsignal ST_(p′+1), and the q'th enable signal EN_(q).

The output signal ST_(p′+1) is inverted by the NOR circuit 214 shown inFIG. 16, and input to the input side of the (p′, q)'th NAND circuit 213.The output signal ST_(p′) and the q'th enable signal EN_(q) are directlyinput to the input side of the (p′, q)'th NAND circuit 213.

With the second embodiment, the first period identifying signal SP₁ isdirectly input to the input side of the (1, 1)'th through (4, 2)'th NANDcircuits 213, and the second period identifying signal SP₂ is alsodirectly input. The first period identifying signal SP₁ is directlyinput to the input side of the (5, 1)'th through (8, 2)'th NAND circuits213, and the second period identifying signal SP₂ inverted by a NORcircuit 216 shown in FIG. 16 is input.

Also, the first period identifying signal SP₁ is inverted by a NORcircuit 217 shown in FIG. 16 and input to the input side of the (9,1)'th through (12, 2)'th NAND circuits 213, and the second periodidentifying signal SP₂ is directly input. The first period identifyingsignal SP₁ is inverted by the NOR circuit 217 and input to the inputside of the (13, 1)'th through (16, 2)'th NAND circuits 213, and thesecond period identifying signal SP₂ is inverted by the NOR circuit 216and is input.

Let us consider the (8, 1)'th NAND circuit 213. Signals based on thescanning signals from the (8, 1)'th NAND circuit 213 are supplied to thescanning line SCL₁₄. As shown in FIG. 16, in the period T₁₇ in which thescanning signal should be generated, the output signal ST₈, the signalobtained by inverting the output signal ST₉, and the first enable signalEN₁, are at high level. However, the first stage shift register SR₁ hasalso received input of the second start pulse through fourth start pulsein addition to the first start pulse, so the output signal ST₈, thesignal obtained by inverting the output signal ST₉, and the first enablesignal EN₁, are at high level in periods T₁, T₉, and T₂₅, as well.

Accordingly, if the (8, 1)'th NAND circuit 213 were to operate basedonly on the output signal ST₈, a signal obtained by inverting the outputsignal ST₉, and the first enable signal EN₁, trouble would occur in thata scanning signal would be supplied to the scanning line SCL₁₄ not onlyin the period T₁₇ in which the scanning signal should be generated, butalso in the periods T₁, T₉, and T₂₅. However, as described above, thefirst period identifying signal SP₁ is directly input to the input sideof the (8, 1)'th NAND circuit 213, and the second period identifyingsignal SP₂ is inverted and input. In periods T₁, T₉, T₁₇, and T₂₅, theonly period where the first period identifying signal SP₁ is at a highlevel and the second period identifying signal SP₂ is at a low level isthe period T₁₇. Accordingly, the (8, 1)'th NAND circuit 213 generates ascanning signal based only on the output signal ST₈, a signal obtainedby inverting the output signal ST₉, and the first enable signal EN₁.

Let us also consider the (9, 1)'th NAND circuit 213. Signals based onthe scanning signals from the (9, 1)'th NAND circuit 213 are supplied tothe scanning line SCL₁₆ shown in FIG. 1. As shown in FIG. 19, in theperiod T₁₉ in which the scanning signal should be generated, the outputsignal ST₉, the signal obtained by inverting the output signal ST₁₀, andthe first enable signal EN₁, are at high level. However, the first stageshift register SR₁ has also received input of the second start pulsethrough fourth start pulse in addition to the first start pulse, so theoutput signal ST₉, the signal obtained by inverting the output signalST₁₀, and the first enable signal EN₁, are at high level in periods T₃,T₁₁, and T₂₇, as well.

Accordingly, if the (9, 1)'th NAND circuit 213 were to operate basedonly on the output signal ST₉, a signal obtained by inverting the outputsignal ST₁₀, and the first enable signal EN₁, trouble would occur inthat a scanning signal would be supplied to the scanning line SCL₁₆ notonly in the period T₁₉ in which the scanning signal should be generated,but also in the periods T₃, T₁₁, and T₂₇. However, as described above,the first period identifying signal SP₁ is inverted and input to the (9,1)'th NAND circuit 213, and the second period identifying signal SP₂ isdirectly input. In periods T₃, T₁₁, T₁₉, and T₂₇, the only period wherethe first period identifying signal SP₁ is at a low level and the secondperiod identifying signal SP₂ is at a high level is the period T₁₉.Accordingly, the (9, 1)'th NAND circuit 213 generates a scanning signalbased only on the output signal ST₉, a signal obtained by inverting theoutput signal ST₁₀, and the first enable signal EN₁.

While description has been made regarding the operations of the (8,1)'th NAND circuit 213 and the (9, 1)'th NAND circuit 213, theoperations are the same for the other NAND circuits 213 as well. The(p′, q)'th NAND circuit 213 generates a scanning signal based only on aportion of the output signal ST_(p′) corresponding to the first startpulse, the signal obtained by inverting the output signal ST_(p′+1), andthe q'th enable signal EN_(q).

FIG. 20 is a schematic driving timing chart of the display element 10 atthe m'th row and n'th column, corresponding to FIG. 8 in the firstembodiment. In the same way as with the first embodiment, p′=8 and q=1,and m=14, when comparing the timing chart in FIG. 20 with FIGS. 17through 19. Specifically, the timing chart of initialization controlline AZ₁₄, scanning line SCL₁₄, and display control line CL₁₄ in FIG. 18is to be referred to.

The operations of the Period TP(2)⁻² through Period TP(2)₂ shown in FIG.20 are the same as the operations of the Period TP(1)⁻² through PeriodTP(1)₂ described with the first embodiment, so description thereof willbe omitted. Also, Period TP(2)₉ shown in FIG. 20 corresponds to thePeriod TP(1)₉ described with the first embodiment, albeit there bedifferent in the start thereof.

With the first embodiment, the lit period and unlit period switch oncebetween the end of Period TP(1)₂ and the start Period TP(1)₅ in FIG. 8.On the other hand, with the second embodiment, the lit period and unlitperiod switch three times between the end of Period TP(2)₂ and the startPeriod TP(2)₉ in FIG. 20. Accordingly, flickering the image displayed onthe display device is further reduced.

Third Embodiment

The third embodiment also relates to a scan driving circuit and to adisplay device having the scan driving circuit. As shown in FIG. 2, thedisplay device 3 according to the third embodiment is of the sameconfiguration as the display device 1 according to the first embodiment,other than the scan driving circuit being different. Accordingly,description of the display device 3 according to the third embodimentwill be omitted.

FIG. 21 is a circuit diagram of a scan driving circuit 310 according tothe third embodiment, FIG. 22 is a schematic timing chart of a shiftregister unit 311 making up the scan driving circuit 310 shown in FIG.21, FIG. 23 is a schematic timing chart of an upstream stage of a logiccircuit unit 312 making up the scan driving circuit 310 shown in FIG.21, and FIG. 24 is a schematic timing chart of a downstream stage of thelogic circuit unit 312 making up the scan driving circuit 310 shown inFIG. 21.

With the scan driving circuit 110 according to the first embodiment, afirst enable signal EN₁ and second enable signal EN₂ are used. With thescan driving circuit 310 according to the third embodiment, a thirdenable signal EN₃ and fourth enable signal EN₄ are used in addition tothese. Accordingly, the number of stages making up the shift registerunit configuring the scan driving circuit can be reduced as comparedwith the case of the scan driving circuit 110 according to the firstembodiment.

As shown in FIG. 21, the scan driving circuit 310 also includes:

(A) a shift register unit 311 configured of P stages of shift registersSR, to sequentially shift input start pulses STP and output outputsignals ST from each stage; and

(B) a logic circuit unit 312 configured to operate based on outputsignals ST from the shift register unit 311, and enable signals (in thecase of the third embodiment, first enable signal EN₁, second enablesignal EN₂, third enable signal EN₃, and fourth enable signal EN₄).

Representing the output signals of the p'th stage shift register SR_(p)with ST_(p), the start of the start pulse in the output signal ST_(p+1)of the p+1'th stage shift register SR_(p+1) is situated between thestart and end of the start pulse in the output signal ST_(p), as shownin FIG. 22. The shift register unit 311 operates based on the clocksignals CK and start pulse STP so as to satisfy the above conditions.

A first start pulse through a U'th start pulse are input to the firststage shift register SR₁ in a period equivalent to one field period.Note that with the third embodiment, U=2 the same as with the firstembodiment, and the first start pulse and second start pulse are input.

Specifically, the first start pulse input to the first stage shiftregister SR₁ is a pulse which has a leading edge between the start andend of the period T₁ shown in FIG. 22, and which has a trailing edgebetween the start and end of the period T₉. Also, the second start pulseis a pulse which has a leading edge between the start and end of theperiod T₁₇ shown in FIG. 22, and which has a trailing edge between thestart and end of the period T₂₅.

With the first and second embodiments, the clock signal CK is a squarewave signal of which the polarity inverts every two horizontal scanningperiods. Conversely, with the third embodiment, the clock signal CK is asquare wave signal of which the polarity inverts every four horizontalscanning periods.

The first start pulse in the output signal ST₁ of the shift register SR₁is a pulse which has the leading edge thereof at the start of the periodT₃, and has the trailing edge at the end of period T₁₀. The first startpulses in the output signals ST₂, ST₃, and so on, for the shift registerSR₂ and subsequent shift registers, are pulses which have beensequentially shifted by four horizontal scanning periods. The secondstart pulse in the output signal ST₁ of the shift register SR₁ is apulse which has the leading edge thereof at the start of the period T₁₉,and has the trailing edge at the end of period T₂₆. The second startpulses in the output signals ST₂, ST₃, and so on, for the shift registerSR₂ and subsequent shift registers, are pulses which have beensequentially shifted by four horizontal scanning periods.

Also, one each of a first enable signal through a Q'th enable signalexist in sequence between the start of the first start pulse of theoutput signal ST_(p) and the start of the first start pulse of theoutput signal ST_(p+1). In the third embodiment, Q=4, and there are oneeach of the first enable signal EN₁, second enable signal EN₂, thirdenable signal EN₃, and fourth enable signal EN₄ in sequence. In otherwords, the first enable signal EN₁, second enable signal EN₂, thirdenable signal EN₃, and fourth enable signal EN₄ are signals generated soas to satisfy the above conditions, and basically are square wavesignals of the same cycle but with different phases.

Specifically, the first enable signal EN₁ is a square wave signal ofwhich one cycle is four horizontal scanning periods. The second enablesignal EN₂ is a signal of which the phase is delayed as to the firstenable signal EN₁ by one horizontal scanning period. The third enablesignal EN₃ is a signal of which the phase is delayed as to the firstenable signal EN₁ by two horizontal scanning periods. The fourth enablesignal EN₄ is a signal of which the phase is delayed as to the firstenable signal EN₁ by three horizontal scanning periods.

For example, one each of the first enable signal EN₁ in the period T₃,the second enable signal EN₂ in the period T₄, the third enable signalEN₃ in the period T₅, and the fourth enable signal EN₄ in the period T₆,sequentially exist between the start of the start pulse in the outputsignal ST₁ (i.e., start of period T₃) and the start of the start pulsein the output signal ST₂ (i.e., start of period T₇). In the same way,one each of the first enable signal EN₁, second enable signal EN₂, thirdenable signal EN₃, and fourth enable signal EN₄, serially exist betweenthe start of the start pulse in the output signal ST₂ and the start ofthe start pulse in the output signal ST₃.

As shown in FIG. 21, the logic circuit unit 312 has (P−2)×Q NANDcircuits 313. Specifically, the logic circuit unit 312 has (1, 1)'ththrough (P−2, 4)'th NAND circuits 313. Period identifying signals SP foridentifying each period from the start of the u'th start pulse startpulse in an output signal ST₁ to the start of a (u+1) 'th start pulse,and a period from the start of the U'th start pulse to the start of thefirst start pulse in the next frame, are input to the logic circuit unit312.

In the third embodiment, U=2, and the period identifying signal SP is asdescribed with the first embodiment. That is to say, the periodidentifying signal SP is a signal for identifying the period from thestart of the first start pulse in the output signal ST₁ to the start ofthe second start pulse, and the period from the start of the secondstart pulse to the start of the first start pulse in the next frame. Inthe third embodiment as well, the period identifying signal SP is asignal which is at high level during the period from the start of periodT₃ to the end of period T₁₈, and at low level during the period from thestart of period T₁₉ to the end of period T₂ of the next frame.

With a q'th enable signal represented as EN_(q), as shown in FIG. 21signals based on the period identifying signal SP, the output signalST_(p), a signal obtained by inverting the output signal ST_(p+1), andthe q'th enable signal EN_(q), are input to a (p′, q)'th NAND circuit313, whereby the operations of the NAND circuit 313 are restricted basedon the period identifying signal SP, such that the NAND circuit 313generates scanning signals based only on a portion of the output signalST_(p′) corresponding to the first start pulse, the signal obtained byinverting the output signal ST_(p′+1), and the q'th enable signalEN_(q).

The output signal ST_(p′+1) is inverted by the NOR circuit 314 shown inFIG. 21, and input to the input side of the (p′, q)'th NAND circuit 313.The output signal ST_(p′) and the q'th enable signal EN_(q) are directlyinput to the input side of the (p′, q)'th NAND circuit 313.

With the third embodiment, as with the first embodiment, the periodidentifying signal SP is directly input to the input side of the (1,1)'th through (4, 4)'th NAND circuits 313. The period identifying signalSP is inverted by the. NOR circuit 316 and input to the input side ofthe (5, 1)'th through (8, 4)'th NAND circuits 313.

Let us consider the (4, 3)'th NAND circuit 313, for example. Signalsbased on the scanning signals from the (4, 3)'th NAND circuit 313 aresupplied to the scanning line SCL₁₄ shown in FIG. 21. As shown in FIG.23, in the period T₁₇ in which the scanning signal should be generated,the output signal ST₄, the signal obtained by inverting the outputsignal ST₅, and the third enable signal EN₃, are at high level. However,the first stage shift register SR₁ has also received input of the secondstart pulse in addition to the first start pulse, so the output signalST₄, the signal obtained by inverting the output signal ST₅, and thethird enable signal EN₃, are at high level in period T₁ as well.

Accordingly, if the (4, 3)'th NAND circuit 313 were to operate basedonly on the output signal ST₄, a signal obtained by inverting the outputsignal ST₅, and the third enable signal EN₃, trouble would occur in thata scanning signal would be supplied to the scanning line SCL₁₄ not onlyin the period T₁₇ in which the scanning signal should be generated, butalso in the period T₁. However, as described above, the periodidentifying signal SP is directly input to the input side of the (4,3)'th NAND circuit 313. Of periods T₁ and T₁₇, the only period where theperiod identifying signal SP is at a high level is the period T₁₇.Accordingly, the (4, 3)'th NAND circuit 313 generates a scanning signalbased only on the output signal ST₄, a signal obtained by inverting theoutput signal ST₅, and the third enable signal EN₃.

Let us also consider the (5, 1)'th NAND circuit 313. Signals based onthe scanning signals from the (5, 1)'th NAND circuit 313 are supplied tothe scanning line SCL₁₆ shown in FIG. 21. As shown in FIG. 24, in theperiod T₁₉ in which the scanning signal should be generated, the outputsignal ST₅, the signal obtained by inverting the output signal ST₆, andthe first enable signal EN₁, are at high level. However, the first stageshift register SR₁ has also received input of the second start pulse inaddition to the first start pulse, so the output signal ST₅, the signalobtained by inverting the output signal ST₆, and the first enable signalEN₁, are at high level in period T₃ as well.

Accordingly, if the (5, 1)'th NAND circuit 313 were to operate basedonly on the output signal ST₅, a signal obtained by inverting the outputsignal ST₆, and the first enable signal EN₁, trouble would occur in thata scanning signal would be supplied to the scanning line SCL₁₆ not onlyin the period T₁₉ in which the scanning signal should be generated, butalso in the period T₃. However, as described above, the periodidentifying signal SP is inverted and input to the (5, 1)'th NANDcircuit 313. Of periods T₃ and T₁₉, the only period where the periodidentifying signal SP is at a low level is the period T₁₉. Accordingly,the (5, 1)'th NAND circuit 313 generates a scanning signal based only onthe output signal ST₅, a signal obtained by inverting the output signalST₆, and the first enable signal EN₁.

While description has been made regarding the operations of the (4,3)'th NAND circuit 313 and the (5, 1)'th NAND circuit 313, theoperations are the same for the other NAND circuits 313 as well. The(p′, q)'th NAND circuit 313 generates a scanning signal based only on aportion of the output signal ST_(p) corresponding to the first startpulse in the output signal ST_(p), the signal obtained by inverting theoutput signal ST_(p′+1), and the q'th enable signal EN_(q).

FIG. 25 is a schematic driving timing chart of the display element 10 atthe m'th row and n'th column, corresponding to FIG. 8 in the firstembodiment. Here, p′=4 and q=3, and in the same way as with the firstembodiment, m=14, when comparing the timing chart in FIG. 25 with FIGS.22 through 24. Specifically, the timing chart of initialization controlline AZ₁₄, scanning line SCL₁₄, and display control line CL₁₄ in FIG. 23is to be referred to.

The operations of the Period TP(3)⁻² through Period TP(3)₂ shown in FIG.25 are the same as the operations of the Period TP(1)⁻² through PeriodTP(1)₂ described with the first embodiment, so description thereof willbe omitted. Also, the operations of Period TP(3)₃ through Period TP(3)₅shown in FIG. 25 are the same as the operations of Period TP(1)₃ throughPeriod TP(1)₅ described with the first embodiment, albeit there bedifferent in the length of periods thereof, so description thereof willbe omitted.

While the present invention has been described so far with reference topreferred embodiments, the present invention is not restricted by theseembodiments. The configuration and structure of the various componentsconfiguring the scan driving circuit, display device, and displayelements, and the processes in the operations of the display device,described in the embodiments, may be modified as appropriate.

For example, with the driving circuit 11 configuring the display element10 shown in FIG. 6, in the event that the third transistor TR₃ andfourth transistor TR₄ are n-channel type transistors, the NOR circuit115 shown in FIG. 1, the NOR circuit 215 shown in FIG. 16, and the NORcircuit 315 shown in FIG. 21, can be omitted. In this way, the polarityof signals from the scan driving circuit can be suitably set inaccordance with the configuration of the display elements, and suppliedto the scanning lines, initialization control lines, and display controllines.

The present application contains subject matter related to thatdisclosed in Japanese Priority Patent Application JP 2008-182369 filedin the Japan Patent Office on Jul. 14, 2008, the entire content of whichis hereby incorporated by reference.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. A display device comprising: (1) display elementsarrayed in the form of a two-dimensional matrix; (2) scanning lines,initialization control lines configured to initialize said displayelements, and display control lines configured to control lit/unlitstates of said display elements, said scanning lines, initializationcontrol lines, and display control lines extending in a first direction;(3) data lines extending in a second direction different from said firstdirection; and (4) a scan driving circuit; said scan driving circuitincluding (A) a shift register unit configured of P (wherein P is anatural number of 3 or greater) stages of shift registers, tosequentially shift input start pulses and output output signals fromeach stage, and (B) a logic circuit unit configured to operate based onoutput signals from said shift register unit, and enable signals, (C)where, with the output signals of a p'th (where p=1, 2, . . . P−1) stageshift register represented as ST_(p), the start of a start pulse of anoutput signal ST_(p+1) of a p+1'th shift register is situated betweenthe start and end of a start pulse of the output signal ST_(p), (D) andwhere one each of a first enable signal through a Q'th enable signal(where Q is a natural number of 2 or greater) exist in sequence betweenthe start of the start pulse of the output signal ST_(p) and the startof the start pulse of the output signal ST_(p+1), (E) and wherein saidlogic circuit unit includes (P−2)×Q NAND circuits; wherein a first startpulse through a U'th (where U is a natural number of 2 or greater) startpulse are input to a first stage shift register during a periodequivalent to one field period; and wherein period identifying signalsare input to said logic circuit unit to identify each period from a u'th(where u=1, 2, . . . U−1) start pulse in an output signal ST₁ to au+1'th start pulse, and a period from the start of the U'th start pulseto the start of the first start pulse in the next frame; and wherein,with a q'th enable signal (where q=1, 2, . . . Q−1) represented asEN_(q), a signal based on a period identifying signal, the output signalST_(p), a signal obtained by inverting the output signal ST_(p+1), andthe q'th enable signal EN_(q), are input to a (p′, q)'th NAND circuit;and wherein the operations of said NAND circuit are restricted based onperiod identifying signals, such that said NAND circuit generatesscanning signals based only on a portion of the output signal ST_(p)corresponding to the first start pulse, the signal obtained by invertingthe output signal ST_(p+1), and the q'th enable signal EN_(q), andwherein, with regard to a display element receiving supply of signalsbased on scanning signals from the (p′, q)'th NAND circuit (except for acase wherein (p′=1, q=1) via a scanning line, a signal based on ascanning signal from a (p′−1, q′)'th (wherein q is a natural number from1 through Q) NAND circuit, in the event that q=1 holds, and a signalbased on a scanning signal from a (p′, q″)'th (wherein q″ is a naturalnumber from 1 through (q−1)) NAND circuit, in the event that q>1 holds,are supplied from an initialization control line connected to saiddisplay element, and a signal based on the output signal ST_(p+1) from ap′+1'th shift register, in the event that q=1 holds, and a signal basedon an output signal ST_(p+2) from a p′+2'th shift register, in the eventthat q>1 holds, are supplied from a display control line connected tosaid display element.
 2. The display device according to claim 1,wherein, with regard to a display element receiving supply of signalsbased on scanning signals from the (p′, q)'th NAND circuit via ascanning line, a signal based on a scanning signal from a (p′−1, Q′)'thNAND circuit, in the event that q=1 holds, and a signal based on ascanning signal from a (p′, q−1)'th NAND circuit, in the event that q>1holds, are supplied from an initialization control line connected tosaid display element.
 3. The display device according to claim 1, eachof said display elements comprising: (1-1) a driving circuit including awrite transistor, a driving transistor, and a capacitance unit; and(1-2) a light emitting unit to which current is applied via said drivingtransistor.
 4. The display device according to claim 3, wherein saidlight-emitting unit is configured of an organic electroluminescenceunit.
 5. The display device according to claim 3, wherein, with regardto said write transistor, (a-1) one source/drain region is connected tothe data line, and (a-2) the gate electrode is connected to the scanningline; and wherein, with regard to said driving transistor, (b-1) onesource/drain region is connected to the other source/drain region ofsaid write transistor, thereby configuring a first node; and wherein,with regard to said capacitance unit, (c-1) a predetermined referencevoltage is applied to one end thereof, and (c-2) the other end isconnected with the gate electrode of the driving transistor, therebyconfiguring a second node; and wherein said write transistor iscontrolled by signals from the scanning line.
 6. The display deviceaccording to claim 5, said driving circuit further comprising: (d) afirst switch circuit unit connected between said second node and theother source/drain region of said driving transistor; wherein said firstswitch circuit unit is controlled by signals from the scanning line. 7.The display device according to claim 5, said driving circuit furthercomprising: (e) a second switch circuit unit connected between saidsecond node and a power supply line to which a predeterminedinitialization voltage is applied; wherein said second switch circuitunit is controlled by signals from the initialization control line. 8.The display device according to claim 5, said driving circuit furthercomprising: (f) a third switch circuit unit connected between said firstnode and a power supply line to which a driving voltage is applied;wherein said third switch circuit unit is controlled by signals from thedisplay control line.
 9. The display device according to claim 5, saiddriving circuit further comprising: (g) a fourth switch circuit unitconnected between the other source/drain region of said drivingtransistor and one end of said light emitting unit; wherein said fourthswitch circuit unit is controlled by signals from the display controlline.
 10. A driving circuit comprising: (A) a shift register unitconfigured of P (wherein P is a natural number of 3 or greater) stagesof shift registers, to sequentially shift input start pulses and outputoutput signals from each stage, and (B) a logic circuit unit configuredto operate based on output signals from said shift register unit, andenable signals, (C) where, with the output signals of a p'th (where p=1,2, . . . P−1) stage shift register represented as ST_(p), the start of astart pulse of an output signal ST_(p+1) of a p+1'th shift register issituated between the start and end of a start pulse of the output signalST_(p), (D) and where one each of a first enable signal through a Q'thenable signal (where Q is a natural number of 2 or greater) exist insequence between the start of the start pulse of the output signalST_(p) and the start of the start pulse of the output signal ST_(p+1),(E) and wherein said logic circuit unit includes (P−2)×Q NAND circuits;wherein a first start pulse through a U'th (where U is a natural numberof 2 or greater) start pulse are input to a first stage shift registerduring a period equivalent to one field period; and wherein periodidentifying signals are input to said logic circuit unit to identifyeach period from a u'th (where u=1, 2, . . . U−1) start pulse in anoutput signal ST₁ to a u+1'th start pulse, and a period from the startof the U'th start pulse to the start of the first start pulse in thenext frame; and wherein, with a q'th enable signal (where q=1, 2, . . .Q−1) represented as EN_(q), a signal based on a period identifyingsignal, the output signal ST_(p), a signal obtained by inverting theoutput signal ST_(p+1), and the q'th enable signal EN_(q), are input toa (p′, q)'th NAND circuit; and wherein the operations of said NANDcircuit are restricted based on period identifying signals, such thatsaid NAND circuit generates scanning signals based only on a portion ofthe output signal ST_(p) corresponding to the first start pulse, thesignal obtained by inverting the output signal ST_(p+1), and the q'thenable signal EN_(q).